1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __ASM_INSN_DEF_H 4 #define __ASM_INSN_DEF_H 5 6 #include <asm/asm.h> 7 8 #define INSN_R_FUNC7_SHIFT 25 9 #define INSN_R_RS2_SHIFT 20 10 #define INSN_R_RS1_SHIFT 15 11 #define INSN_R_FUNC3_SHIFT 12 12 #define INSN_R_RD_SHIFT 7 13 #define INSN_R_OPCODE_SHIFT 0 14 15 #ifdef __ASSEMBLY__ 16 17 #ifdef CONFIG_AS_HAS_INSN 18 19 .macro insn_r, opcode, func3, func7, rd, rs1, rs2 20 .insn r \opcode, \func3, \func7, \rd, \rs1, \rs2 21 .endm 22 23 #else 24 25 #include <asm/gpr-num.h> 26 27 .macro insn_r, opcode, func3, func7, rd, rs1, rs2 28 .4byte ((\opcode << INSN_R_OPCODE_SHIFT) | \ 29 (\func3 << INSN_R_FUNC3_SHIFT) | \ 30 (\func7 << INSN_R_FUNC7_SHIFT) | \ 31 (.L__gpr_num_\rd << INSN_R_RD_SHIFT) | \ 32 (.L__gpr_num_\rs1 << INSN_R_RS1_SHIFT) | \ 33 (.L__gpr_num_\rs2 << INSN_R_RS2_SHIFT)) 34 .endm 35 36 #endif 37 38 #define __INSN_R(...) insn_r __VA_ARGS__ 39 40 #else /* ! __ASSEMBLY__ */ 41 42 #ifdef CONFIG_AS_HAS_INSN 43 44 #define __INSN_R(opcode, func3, func7, rd, rs1, rs2) \ 45 ".insn r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n" 46 47 #else 48 49 #include <linux/stringify.h> 50 #include <asm/gpr-num.h> 51 52 #define DEFINE_INSN_R \ 53 __DEFINE_ASM_GPR_NUMS \ 54 " .macro insn_r, opcode, func3, func7, rd, rs1, rs2\n" \ 55 " .4byte ((\\opcode << " __stringify(INSN_R_OPCODE_SHIFT) ") |" \ 56 " (\\func3 << " __stringify(INSN_R_FUNC3_SHIFT) ") |" \ 57 " (\\func7 << " __stringify(INSN_R_FUNC7_SHIFT) ") |" \ 58 " (.L__gpr_num_\\rd << " __stringify(INSN_R_RD_SHIFT) ") |" \ 59 " (.L__gpr_num_\\rs1 << " __stringify(INSN_R_RS1_SHIFT) ") |" \ 60 " (.L__gpr_num_\\rs2 << " __stringify(INSN_R_RS2_SHIFT) "))\n" \ 61 " .endm\n" 62 63 #define UNDEFINE_INSN_R \ 64 " .purgem insn_r\n" 65 66 #define __INSN_R(opcode, func3, func7, rd, rs1, rs2) \ 67 DEFINE_INSN_R \ 68 "insn_r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n" \ 69 UNDEFINE_INSN_R 70 71 #endif 72 73 #endif /* ! __ASSEMBLY__ */ 74 75 #define INSN_R(opcode, func3, func7, rd, rs1, rs2) \ 76 __INSN_R(RV_##opcode, RV_##func3, RV_##func7, \ 77 RV_##rd, RV_##rs1, RV_##rs2) 78 79 #define RV_OPCODE(v) __ASM_STR(v) 80 #define RV_FUNC3(v) __ASM_STR(v) 81 #define RV_FUNC7(v) __ASM_STR(v) 82 #define RV_RD(v) __ASM_STR(v) 83 #define RV_RS1(v) __ASM_STR(v) 84 #define RV_RS2(v) __ASM_STR(v) 85 #define __RV_REG(v) __ASM_STR(x ## v) 86 #define RV___RD(v) __RV_REG(v) 87 #define RV___RS1(v) __RV_REG(v) 88 #define RV___RS2(v) __RV_REG(v) 89 90 #define RV_OPCODE_SYSTEM RV_OPCODE(115) 91 92 #define HFENCE_VVMA(vaddr, asid) \ 93 INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(17), \ 94 __RD(0), RS1(vaddr), RS2(asid)) 95 96 #define HFENCE_GVMA(gaddr, vmid) \ 97 INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(49), \ 98 __RD(0), RS1(gaddr), RS2(vmid)) 99 100 #define HLVX_HU(dest, addr) \ 101 INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(50), \ 102 RD(dest), RS1(addr), __RS2(3)) 103 104 #define HLV_W(dest, addr) \ 105 INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(52), \ 106 RD(dest), RS1(addr), __RS2(0)) 107 108 #ifdef CONFIG_64BIT 109 #define HLV_D(dest, addr) \ 110 INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(54), \ 111 RD(dest), RS1(addr), __RS2(0)) 112 #else 113 #define HLV_D(dest, addr) \ 114 __ASM_STR(.error "hlv.d requires 64-bit support") 115 #endif 116 117 #define SINVAL_VMA(vaddr, asid) \ 118 INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(11), \ 119 __RD(0), RS1(vaddr), RS2(asid)) 120 121 #define SFENCE_W_INVAL() \ 122 INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(12), \ 123 __RD(0), __RS1(0), __RS2(0)) 124 125 #define SFENCE_INVAL_IR() \ 126 INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(12), \ 127 __RD(0), __RS1(0), __RS2(1)) 128 129 #define HINVAL_VVMA(vaddr, asid) \ 130 INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(19), \ 131 __RD(0), RS1(vaddr), RS2(asid)) 132 133 #define HINVAL_GVMA(gaddr, vmid) \ 134 INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(51), \ 135 __RD(0), RS1(gaddr), RS2(vmid)) 136 137 #endif /* __ASM_INSN_DEF_H */ 138