1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef __ASM_IMAGE_H 4 #define __ASM_IMAGE_H 5 6 #define RISCV_IMAGE_MAGIC "RISCV" 7 8 #define RISCV_IMAGE_FLAG_BE_SHIFT 0 9 #define RISCV_IMAGE_FLAG_BE_MASK 0x1 10 11 #define RISCV_IMAGE_FLAG_LE 0 12 #define RISCV_IMAGE_FLAG_BE 1 13 14 #ifdef CONFIG_CPU_BIG_ENDIAN 15 #error conversion of header fields to LE not yet implemented 16 #else 17 #define __HEAD_FLAG_BE RISCV_IMAGE_FLAG_LE 18 #endif 19 20 #define __HEAD_FLAG(field) (__HEAD_FLAG_##field << \ 21 RISCV_IMAGE_FLAG_##field##_SHIFT) 22 23 #define __HEAD_FLAGS (__HEAD_FLAG(BE)) 24 25 #define RISCV_HEADER_VERSION_MAJOR 0 26 #define RISCV_HEADER_VERSION_MINOR 1 27 28 #define RISCV_HEADER_VERSION (RISCV_HEADER_VERSION_MAJOR << 16 | \ 29 RISCV_HEADER_VERSION_MINOR) 30 31 #ifndef __ASSEMBLY__ 32 /** 33 * struct riscv_image_header - riscv kernel image header 34 * @code0: Executable code 35 * @code1: Executable code 36 * @text_offset: Image load offset (little endian) 37 * @image_size: Effective Image size (little endian) 38 * @flags: kernel flags (little endian) 39 * @version: version 40 * @res1: reserved 41 * @res2: reserved 42 * @magic: Magic number 43 * @res3: reserved (will be used for additional RISC-V specific 44 * header) 45 * @res4: reserved (will be used for PE COFF offset) 46 * 47 * The intention is for this header format to be shared between multiple 48 * architectures to avoid a proliferation of image header formats. 49 */ 50 51 struct riscv_image_header { 52 u32 code0; 53 u32 code1; 54 u64 text_offset; 55 u64 image_size; 56 u64 flags; 57 u32 version; 58 u32 res1; 59 u64 res2; 60 u64 magic; 61 u32 res3; 62 u32 res4; 63 }; 64 #endif /* __ASSEMBLY__ */ 65 #endif /* __ASM_IMAGE_H */ 66