1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copied from arch/arm64/include/asm/hwcap.h 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Copyright (C) 2017 SiFive 7 */ 8 #ifndef _ASM_RISCV_HWCAP_H 9 #define _ASM_RISCV_HWCAP_H 10 11 #include <asm/alternative-macros.h> 12 #include <asm/errno.h> 13 #include <linux/bits.h> 14 #include <uapi/asm/hwcap.h> 15 16 #define RISCV_ISA_EXT_a ('a' - 'a') 17 #define RISCV_ISA_EXT_c ('c' - 'a') 18 #define RISCV_ISA_EXT_d ('d' - 'a') 19 #define RISCV_ISA_EXT_f ('f' - 'a') 20 #define RISCV_ISA_EXT_h ('h' - 'a') 21 #define RISCV_ISA_EXT_i ('i' - 'a') 22 #define RISCV_ISA_EXT_m ('m' - 'a') 23 #define RISCV_ISA_EXT_s ('s' - 'a') 24 #define RISCV_ISA_EXT_u ('u' - 'a') 25 26 /* 27 * These macros represent the logical IDs of each multi-letter RISC-V ISA 28 * extension and are used in the ISA bitmap. The logical IDs start from 29 * RISCV_ISA_EXT_BASE, which allows the 0-25 range to be reserved for single 30 * letter extensions. The maximum, RISCV_ISA_EXT_MAX, is defined in order 31 * to allocate the bitmap and may be increased when necessary. 32 * 33 * New extensions should just be added to the bottom, rather than added 34 * alphabetically, in order to avoid unnecessary shuffling. 35 */ 36 #define RISCV_ISA_EXT_BASE 26 37 38 #define RISCV_ISA_EXT_SSCOFPMF 26 39 #define RISCV_ISA_EXT_SSTC 27 40 #define RISCV_ISA_EXT_SVINVAL 28 41 #define RISCV_ISA_EXT_SVPBMT 29 42 #define RISCV_ISA_EXT_ZBB 30 43 #define RISCV_ISA_EXT_ZICBOM 31 44 #define RISCV_ISA_EXT_ZIHINTPAUSE 32 45 46 #define RISCV_ISA_EXT_MAX 64 47 #define RISCV_ISA_EXT_NAME_LEN_MAX 32 48 49 #ifndef __ASSEMBLY__ 50 51 #include <linux/jump_label.h> 52 53 struct riscv_isa_ext_data { 54 /* Name of the extension displayed to userspace via /proc/cpuinfo */ 55 char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; 56 /* The logical ISA extension ID */ 57 unsigned int isa_ext_id; 58 }; 59 60 static __always_inline bool 61 riscv_has_extension_likely(const unsigned long ext) 62 { 63 compiletime_assert(ext < RISCV_ISA_EXT_MAX, 64 "ext must be < RISCV_ISA_EXT_MAX"); 65 66 asm_volatile_goto( 67 ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1) 68 : 69 : [ext] "i" (ext) 70 : 71 : l_no); 72 73 return true; 74 l_no: 75 return false; 76 } 77 78 static __always_inline bool 79 riscv_has_extension_unlikely(const unsigned long ext) 80 { 81 compiletime_assert(ext < RISCV_ISA_EXT_MAX, 82 "ext must be < RISCV_ISA_EXT_MAX"); 83 84 asm_volatile_goto( 85 ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1) 86 : 87 : [ext] "i" (ext) 88 : 89 : l_yes); 90 91 return false; 92 l_yes: 93 return true; 94 } 95 96 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); 97 98 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) 99 100 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit); 101 #define riscv_isa_extension_available(isa_bitmap, ext) \ 102 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext) 103 104 #endif 105 106 #endif /* _ASM_RISCV_HWCAP_H */ 107