1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copied from arch/arm64/include/asm/hwcap.h 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Copyright (C) 2017 SiFive 7 */ 8 #ifndef _ASM_RISCV_HWCAP_H 9 #define _ASM_RISCV_HWCAP_H 10 11 #include <asm/alternative-macros.h> 12 #include <asm/errno.h> 13 #include <linux/bits.h> 14 #include <uapi/asm/hwcap.h> 15 16 #define RISCV_ISA_EXT_a ('a' - 'a') 17 #define RISCV_ISA_EXT_c ('c' - 'a') 18 #define RISCV_ISA_EXT_d ('d' - 'a') 19 #define RISCV_ISA_EXT_f ('f' - 'a') 20 #define RISCV_ISA_EXT_h ('h' - 'a') 21 #define RISCV_ISA_EXT_i ('i' - 'a') 22 #define RISCV_ISA_EXT_m ('m' - 'a') 23 #define RISCV_ISA_EXT_s ('s' - 'a') 24 #define RISCV_ISA_EXT_u ('u' - 'a') 25 #define RISCV_ISA_EXT_v ('v' - 'a') 26 27 /* 28 * These macros represent the logical IDs of each multi-letter RISC-V ISA 29 * extension and are used in the ISA bitmap. The logical IDs start from 30 * RISCV_ISA_EXT_BASE, which allows the 0-25 range to be reserved for single 31 * letter extensions. The maximum, RISCV_ISA_EXT_MAX, is defined in order 32 * to allocate the bitmap and may be increased when necessary. 33 * 34 * New extensions should just be added to the bottom, rather than added 35 * alphabetically, in order to avoid unnecessary shuffling. 36 */ 37 #define RISCV_ISA_EXT_BASE 26 38 39 #define RISCV_ISA_EXT_SSCOFPMF 26 40 #define RISCV_ISA_EXT_SSTC 27 41 #define RISCV_ISA_EXT_SVINVAL 28 42 #define RISCV_ISA_EXT_SVPBMT 29 43 #define RISCV_ISA_EXT_ZBB 30 44 #define RISCV_ISA_EXT_ZICBOM 31 45 #define RISCV_ISA_EXT_ZIHINTPAUSE 32 46 #define RISCV_ISA_EXT_SVNAPOT 33 47 #define RISCV_ISA_EXT_ZICBOZ 34 48 #define RISCV_ISA_EXT_SMAIA 35 49 #define RISCV_ISA_EXT_SSAIA 36 50 #define RISCV_ISA_EXT_ZBA 37 51 #define RISCV_ISA_EXT_ZBS 38 52 #define RISCV_ISA_EXT_ZICNTR 39 53 #define RISCV_ISA_EXT_ZICSR 40 54 #define RISCV_ISA_EXT_ZIFENCEI 41 55 #define RISCV_ISA_EXT_ZIHPM 42 56 57 #define RISCV_ISA_EXT_MAX 64 58 #define RISCV_ISA_EXT_NAME_LEN_MAX 32 59 60 #ifdef CONFIG_RISCV_M_MODE 61 #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA 62 #else 63 #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA 64 #endif 65 66 #ifndef __ASSEMBLY__ 67 68 #include <linux/jump_label.h> 69 70 unsigned long riscv_get_elf_hwcap(void); 71 72 struct riscv_isa_ext_data { 73 /* Name of the extension displayed to userspace via /proc/cpuinfo */ 74 char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; 75 /* The logical ISA extension ID */ 76 unsigned int isa_ext_id; 77 }; 78 79 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); 80 81 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) 82 83 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit); 84 #define riscv_isa_extension_available(isa_bitmap, ext) \ 85 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext) 86 87 static __always_inline bool 88 riscv_has_extension_likely(const unsigned long ext) 89 { 90 compiletime_assert(ext < RISCV_ISA_EXT_MAX, 91 "ext must be < RISCV_ISA_EXT_MAX"); 92 93 if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { 94 asm_volatile_goto( 95 ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1) 96 : 97 : [ext] "i" (ext) 98 : 99 : l_no); 100 } else { 101 if (!__riscv_isa_extension_available(NULL, ext)) 102 goto l_no; 103 } 104 105 return true; 106 l_no: 107 return false; 108 } 109 110 static __always_inline bool 111 riscv_has_extension_unlikely(const unsigned long ext) 112 { 113 compiletime_assert(ext < RISCV_ISA_EXT_MAX, 114 "ext must be < RISCV_ISA_EXT_MAX"); 115 116 if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { 117 asm_volatile_goto( 118 ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1) 119 : 120 : [ext] "i" (ext) 121 : 122 : l_yes); 123 } else { 124 if (__riscv_isa_extension_available(NULL, ext)) 125 goto l_yes; 126 } 127 128 return false; 129 l_yes: 130 return true; 131 } 132 133 #endif 134 135 #endif /* _ASM_RISCV_HWCAP_H */ 136