1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copied from arch/arm64/include/asm/hwcap.h 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Copyright (C) 2017 SiFive 7 */ 8 #ifndef _ASM_RISCV_HWCAP_H 9 #define _ASM_RISCV_HWCAP_H 10 11 #include <asm/alternative-macros.h> 12 #include <asm/errno.h> 13 #include <linux/bits.h> 14 #include <uapi/asm/hwcap.h> 15 16 #define RISCV_ISA_EXT_a ('a' - 'a') 17 #define RISCV_ISA_EXT_c ('c' - 'a') 18 #define RISCV_ISA_EXT_d ('d' - 'a') 19 #define RISCV_ISA_EXT_f ('f' - 'a') 20 #define RISCV_ISA_EXT_h ('h' - 'a') 21 #define RISCV_ISA_EXT_i ('i' - 'a') 22 #define RISCV_ISA_EXT_m ('m' - 'a') 23 #define RISCV_ISA_EXT_s ('s' - 'a') 24 #define RISCV_ISA_EXT_u ('u' - 'a') 25 26 /* 27 * These macros represent the logical IDs of each multi-letter RISC-V ISA 28 * extension and are used in the ISA bitmap. The logical IDs start from 29 * RISCV_ISA_EXT_BASE, which allows the 0-25 range to be reserved for single 30 * letter extensions. The maximum, RISCV_ISA_EXT_MAX, is defined in order 31 * to allocate the bitmap and may be increased when necessary. 32 * 33 * New extensions should just be added to the bottom, rather than added 34 * alphabetically, in order to avoid unnecessary shuffling. 35 */ 36 #define RISCV_ISA_EXT_BASE 26 37 38 #define RISCV_ISA_EXT_SSCOFPMF 26 39 #define RISCV_ISA_EXT_SSTC 27 40 #define RISCV_ISA_EXT_SVINVAL 28 41 #define RISCV_ISA_EXT_SVPBMT 29 42 #define RISCV_ISA_EXT_ZBB 30 43 #define RISCV_ISA_EXT_ZICBOM 31 44 #define RISCV_ISA_EXT_ZIHINTPAUSE 32 45 #define RISCV_ISA_EXT_SVNAPOT 33 46 #define RISCV_ISA_EXT_ZICBOZ 34 47 #define RISCV_ISA_EXT_SMAIA 35 48 #define RISCV_ISA_EXT_SSAIA 36 49 50 #define RISCV_ISA_EXT_MAX 64 51 #define RISCV_ISA_EXT_NAME_LEN_MAX 32 52 53 #ifdef CONFIG_RISCV_M_MODE 54 #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA 55 #else 56 #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA 57 #endif 58 59 #ifndef __ASSEMBLY__ 60 61 #include <linux/jump_label.h> 62 63 struct riscv_isa_ext_data { 64 /* Name of the extension displayed to userspace via /proc/cpuinfo */ 65 char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; 66 /* The logical ISA extension ID */ 67 unsigned int isa_ext_id; 68 }; 69 70 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); 71 72 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) 73 74 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit); 75 #define riscv_isa_extension_available(isa_bitmap, ext) \ 76 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext) 77 78 static __always_inline bool 79 riscv_has_extension_likely(const unsigned long ext) 80 { 81 compiletime_assert(ext < RISCV_ISA_EXT_MAX, 82 "ext must be < RISCV_ISA_EXT_MAX"); 83 84 if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { 85 asm_volatile_goto( 86 ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1) 87 : 88 : [ext] "i" (ext) 89 : 90 : l_no); 91 } else { 92 if (!__riscv_isa_extension_available(NULL, ext)) 93 goto l_no; 94 } 95 96 return true; 97 l_no: 98 return false; 99 } 100 101 static __always_inline bool 102 riscv_has_extension_unlikely(const unsigned long ext) 103 { 104 compiletime_assert(ext < RISCV_ISA_EXT_MAX, 105 "ext must be < RISCV_ISA_EXT_MAX"); 106 107 if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { 108 asm_volatile_goto( 109 ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1) 110 : 111 : [ext] "i" (ext) 112 : 113 : l_yes); 114 } else { 115 if (__riscv_isa_extension_available(NULL, ext)) 116 goto l_yes; 117 } 118 119 return false; 120 l_yes: 121 return true; 122 } 123 124 #endif 125 126 #endif /* _ASM_RISCV_HWCAP_H */ 127