1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copied from arch/arm64/include/asm/hwcap.h 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Copyright (C) 2017 SiFive 7 */ 8 #ifndef _ASM_RISCV_HWCAP_H 9 #define _ASM_RISCV_HWCAP_H 10 11 #include <asm/alternative-macros.h> 12 #include <asm/errno.h> 13 #include <linux/bits.h> 14 #include <uapi/asm/hwcap.h> 15 16 #define RISCV_ISA_EXT_a ('a' - 'a') 17 #define RISCV_ISA_EXT_b ('b' - 'a') 18 #define RISCV_ISA_EXT_c ('c' - 'a') 19 #define RISCV_ISA_EXT_d ('d' - 'a') 20 #define RISCV_ISA_EXT_f ('f' - 'a') 21 #define RISCV_ISA_EXT_h ('h' - 'a') 22 #define RISCV_ISA_EXT_i ('i' - 'a') 23 #define RISCV_ISA_EXT_j ('j' - 'a') 24 #define RISCV_ISA_EXT_k ('k' - 'a') 25 #define RISCV_ISA_EXT_m ('m' - 'a') 26 #define RISCV_ISA_EXT_p ('p' - 'a') 27 #define RISCV_ISA_EXT_q ('q' - 'a') 28 #define RISCV_ISA_EXT_s ('s' - 'a') 29 #define RISCV_ISA_EXT_u ('u' - 'a') 30 #define RISCV_ISA_EXT_v ('v' - 'a') 31 32 /* 33 * These macros represent the logical IDs of each multi-letter RISC-V ISA 34 * extension and are used in the ISA bitmap. The logical IDs start from 35 * RISCV_ISA_EXT_BASE, which allows the 0-25 range to be reserved for single 36 * letter extensions. The maximum, RISCV_ISA_EXT_MAX, is defined in order 37 * to allocate the bitmap and may be increased when necessary. 38 * 39 * New extensions should just be added to the bottom, rather than added 40 * alphabetically, in order to avoid unnecessary shuffling. 41 */ 42 #define RISCV_ISA_EXT_BASE 26 43 44 #define RISCV_ISA_EXT_SSCOFPMF 26 45 #define RISCV_ISA_EXT_SSTC 27 46 #define RISCV_ISA_EXT_SVINVAL 28 47 #define RISCV_ISA_EXT_SVPBMT 29 48 #define RISCV_ISA_EXT_ZBB 30 49 #define RISCV_ISA_EXT_ZICBOM 31 50 #define RISCV_ISA_EXT_ZIHINTPAUSE 32 51 #define RISCV_ISA_EXT_SVNAPOT 33 52 #define RISCV_ISA_EXT_ZICBOZ 34 53 #define RISCV_ISA_EXT_SMAIA 35 54 #define RISCV_ISA_EXT_SSAIA 36 55 #define RISCV_ISA_EXT_ZBA 37 56 #define RISCV_ISA_EXT_ZBS 38 57 #define RISCV_ISA_EXT_ZICNTR 39 58 #define RISCV_ISA_EXT_ZICSR 40 59 #define RISCV_ISA_EXT_ZIFENCEI 41 60 #define RISCV_ISA_EXT_ZIHPM 42 61 62 #define RISCV_ISA_EXT_MAX 64 63 64 #ifdef CONFIG_RISCV_M_MODE 65 #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA 66 #else 67 #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA 68 #endif 69 70 #ifndef __ASSEMBLY__ 71 72 #include <linux/jump_label.h> 73 #include <asm/cpufeature.h> 74 75 unsigned long riscv_get_elf_hwcap(void); 76 77 struct riscv_isa_ext_data { 78 const unsigned int id; 79 const char *name; 80 const char *property; 81 }; 82 83 extern const struct riscv_isa_ext_data riscv_isa_ext[]; 84 extern const size_t riscv_isa_ext_count; 85 extern bool riscv_isa_fallback; 86 87 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); 88 89 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) 90 91 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit); 92 #define riscv_isa_extension_available(isa_bitmap, ext) \ 93 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext) 94 95 static __always_inline bool 96 riscv_has_extension_likely(const unsigned long ext) 97 { 98 compiletime_assert(ext < RISCV_ISA_EXT_MAX, 99 "ext must be < RISCV_ISA_EXT_MAX"); 100 101 if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { 102 asm goto( 103 ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1) 104 : 105 : [ext] "i" (ext) 106 : 107 : l_no); 108 } else { 109 if (!__riscv_isa_extension_available(NULL, ext)) 110 goto l_no; 111 } 112 113 return true; 114 l_no: 115 return false; 116 } 117 118 static __always_inline bool 119 riscv_has_extension_unlikely(const unsigned long ext) 120 { 121 compiletime_assert(ext < RISCV_ISA_EXT_MAX, 122 "ext must be < RISCV_ISA_EXT_MAX"); 123 124 if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { 125 asm goto( 126 ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1) 127 : 128 : [ext] "i" (ext) 129 : 130 : l_yes); 131 } else { 132 if (__riscv_isa_extension_available(NULL, ext)) 133 goto l_yes; 134 } 135 136 return false; 137 l_yes: 138 return true; 139 } 140 141 static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext) 142 { 143 if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext)) 144 return true; 145 146 return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); 147 } 148 149 static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsigned long ext) 150 { 151 if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext)) 152 return true; 153 154 return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); 155 } 156 #endif 157 158 #endif /* _ASM_RISCV_HWCAP_H */ 159