1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_CSR_H 7 #define _ASM_RISCV_CSR_H 8 9 #include <asm/asm.h> 10 #include <linux/const.h> 11 12 /* Status register flags */ 13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ 14 #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */ 15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ 16 #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */ 17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ 18 #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ 19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ 20 21 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ 22 #define SR_FS_OFF _AC(0x00000000, UL) 23 #define SR_FS_INITIAL _AC(0x00002000, UL) 24 #define SR_FS_CLEAN _AC(0x00004000, UL) 25 #define SR_FS_DIRTY _AC(0x00006000, UL) 26 27 #define SR_XS _AC(0x00018000, UL) /* Extension Status */ 28 #define SR_XS_OFF _AC(0x00000000, UL) 29 #define SR_XS_INITIAL _AC(0x00008000, UL) 30 #define SR_XS_CLEAN _AC(0x00010000, UL) 31 #define SR_XS_DIRTY _AC(0x00018000, UL) 32 33 #ifndef CONFIG_64BIT 34 #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ 35 #else 36 #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ 37 #endif 38 39 /* SATP flags */ 40 #ifndef CONFIG_64BIT 41 #define SATP_PPN _AC(0x003FFFFF, UL) 42 #define SATP_MODE_32 _AC(0x80000000, UL) 43 #define SATP_MODE SATP_MODE_32 44 #else 45 #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) 46 #define SATP_MODE_39 _AC(0x8000000000000000, UL) 47 #define SATP_MODE SATP_MODE_39 48 #endif 49 50 /* Exception cause high bit - is an interrupt if set */ 51 #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) 52 53 /* Interrupt causes (minus the high bit) */ 54 #define IRQ_S_SOFT 1 55 #define IRQ_M_SOFT 3 56 #define IRQ_S_TIMER 5 57 #define IRQ_M_TIMER 7 58 #define IRQ_S_EXT 9 59 #define IRQ_M_EXT 11 60 61 /* Exception causes */ 62 #define EXC_INST_MISALIGNED 0 63 #define EXC_INST_ACCESS 1 64 #define EXC_BREAKPOINT 3 65 #define EXC_LOAD_ACCESS 5 66 #define EXC_STORE_ACCESS 7 67 #define EXC_SYSCALL 8 68 #define EXC_INST_PAGE_FAULT 12 69 #define EXC_LOAD_PAGE_FAULT 13 70 #define EXC_STORE_PAGE_FAULT 15 71 72 /* PMP configuration */ 73 #define PMP_R 0x01 74 #define PMP_W 0x02 75 #define PMP_X 0x04 76 #define PMP_A 0x18 77 #define PMP_A_TOR 0x08 78 #define PMP_A_NA4 0x10 79 #define PMP_A_NAPOT 0x18 80 #define PMP_L 0x80 81 82 /* symbolic CSR names: */ 83 #define CSR_CYCLE 0xc00 84 #define CSR_TIME 0xc01 85 #define CSR_INSTRET 0xc02 86 #define CSR_CYCLEH 0xc80 87 #define CSR_TIMEH 0xc81 88 #define CSR_INSTRETH 0xc82 89 90 #define CSR_SSTATUS 0x100 91 #define CSR_SIE 0x104 92 #define CSR_STVEC 0x105 93 #define CSR_SCOUNTEREN 0x106 94 #define CSR_SSCRATCH 0x140 95 #define CSR_SEPC 0x141 96 #define CSR_SCAUSE 0x142 97 #define CSR_STVAL 0x143 98 #define CSR_SIP 0x144 99 #define CSR_SATP 0x180 100 101 #define CSR_MSTATUS 0x300 102 #define CSR_MISA 0x301 103 #define CSR_MIE 0x304 104 #define CSR_MTVEC 0x305 105 #define CSR_MSCRATCH 0x340 106 #define CSR_MEPC 0x341 107 #define CSR_MCAUSE 0x342 108 #define CSR_MTVAL 0x343 109 #define CSR_MIP 0x344 110 #define CSR_PMPCFG0 0x3a0 111 #define CSR_PMPADDR0 0x3b0 112 #define CSR_MHARTID 0xf14 113 114 #ifdef CONFIG_RISCV_M_MODE 115 # define CSR_STATUS CSR_MSTATUS 116 # define CSR_IE CSR_MIE 117 # define CSR_TVEC CSR_MTVEC 118 # define CSR_SCRATCH CSR_MSCRATCH 119 # define CSR_EPC CSR_MEPC 120 # define CSR_CAUSE CSR_MCAUSE 121 # define CSR_TVAL CSR_MTVAL 122 # define CSR_IP CSR_MIP 123 124 # define SR_IE SR_MIE 125 # define SR_PIE SR_MPIE 126 # define SR_PP SR_MPP 127 128 # define RV_IRQ_SOFT IRQ_M_SOFT 129 # define RV_IRQ_TIMER IRQ_M_TIMER 130 # define RV_IRQ_EXT IRQ_M_EXT 131 #else /* CONFIG_RISCV_M_MODE */ 132 # define CSR_STATUS CSR_SSTATUS 133 # define CSR_IE CSR_SIE 134 # define CSR_TVEC CSR_STVEC 135 # define CSR_SCRATCH CSR_SSCRATCH 136 # define CSR_EPC CSR_SEPC 137 # define CSR_CAUSE CSR_SCAUSE 138 # define CSR_TVAL CSR_STVAL 139 # define CSR_IP CSR_SIP 140 141 # define SR_IE SR_SIE 142 # define SR_PIE SR_SPIE 143 # define SR_PP SR_SPP 144 145 # define RV_IRQ_SOFT IRQ_S_SOFT 146 # define RV_IRQ_TIMER IRQ_S_TIMER 147 # define RV_IRQ_EXT IRQ_S_EXT 148 #endif /* CONFIG_RISCV_M_MODE */ 149 150 /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */ 151 #define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT) 152 #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER) 153 #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT) 154 155 #ifndef __ASSEMBLY__ 156 157 #define csr_swap(csr, val) \ 158 ({ \ 159 unsigned long __v = (unsigned long)(val); \ 160 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ 161 : "=r" (__v) : "rK" (__v) \ 162 : "memory"); \ 163 __v; \ 164 }) 165 166 #define csr_read(csr) \ 167 ({ \ 168 register unsigned long __v; \ 169 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ 170 : "=r" (__v) : \ 171 : "memory"); \ 172 __v; \ 173 }) 174 175 #define csr_write(csr, val) \ 176 ({ \ 177 unsigned long __v = (unsigned long)(val); \ 178 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ 179 : : "rK" (__v) \ 180 : "memory"); \ 181 }) 182 183 #define csr_read_set(csr, val) \ 184 ({ \ 185 unsigned long __v = (unsigned long)(val); \ 186 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ 187 : "=r" (__v) : "rK" (__v) \ 188 : "memory"); \ 189 __v; \ 190 }) 191 192 #define csr_set(csr, val) \ 193 ({ \ 194 unsigned long __v = (unsigned long)(val); \ 195 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ 196 : : "rK" (__v) \ 197 : "memory"); \ 198 }) 199 200 #define csr_read_clear(csr, val) \ 201 ({ \ 202 unsigned long __v = (unsigned long)(val); \ 203 __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ 204 : "=r" (__v) : "rK" (__v) \ 205 : "memory"); \ 206 __v; \ 207 }) 208 209 #define csr_clear(csr, val) \ 210 ({ \ 211 unsigned long __v = (unsigned long)(val); \ 212 __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ 213 : : "rK" (__v) \ 214 : "memory"); \ 215 }) 216 217 #endif /* __ASSEMBLY__ */ 218 219 #endif /* _ASM_RISCV_CSR_H */ 220