1 /* 2 * Copyright (C) 2015 Regents of the University of California 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation, version 2. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #ifndef _ASM_RISCV_CSR_H 15 #define _ASM_RISCV_CSR_H 16 17 #include <asm/asm.h> 18 #include <linux/const.h> 19 20 /* Status register flags */ 21 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ 22 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ 23 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ 24 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ 25 26 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ 27 #define SR_FS_OFF _AC(0x00000000, UL) 28 #define SR_FS_INITIAL _AC(0x00002000, UL) 29 #define SR_FS_CLEAN _AC(0x00004000, UL) 30 #define SR_FS_DIRTY _AC(0x00006000, UL) 31 32 #define SR_XS _AC(0x00018000, UL) /* Extension Status */ 33 #define SR_XS_OFF _AC(0x00000000, UL) 34 #define SR_XS_INITIAL _AC(0x00008000, UL) 35 #define SR_XS_CLEAN _AC(0x00010000, UL) 36 #define SR_XS_DIRTY _AC(0x00018000, UL) 37 38 #ifndef CONFIG_64BIT 39 #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ 40 #else 41 #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ 42 #endif 43 44 /* SATP flags */ 45 #ifndef CONFIG_64BIT 46 #define SATP_PPN _AC(0x003FFFFF, UL) 47 #define SATP_MODE_32 _AC(0x80000000, UL) 48 #define SATP_MODE SATP_MODE_32 49 #else 50 #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) 51 #define SATP_MODE_39 _AC(0x8000000000000000, UL) 52 #define SATP_MODE SATP_MODE_39 53 #endif 54 55 /* SCAUSE */ 56 #define SCAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) 57 58 #define IRQ_U_SOFT 0 59 #define IRQ_S_SOFT 1 60 #define IRQ_M_SOFT 3 61 #define IRQ_U_TIMER 4 62 #define IRQ_S_TIMER 5 63 #define IRQ_M_TIMER 7 64 #define IRQ_U_EXT 8 65 #define IRQ_S_EXT 9 66 #define IRQ_M_EXT 11 67 68 #define EXC_INST_MISALIGNED 0 69 #define EXC_INST_ACCESS 1 70 #define EXC_BREAKPOINT 3 71 #define EXC_LOAD_ACCESS 5 72 #define EXC_STORE_ACCESS 7 73 #define EXC_SYSCALL 8 74 #define EXC_INST_PAGE_FAULT 12 75 #define EXC_LOAD_PAGE_FAULT 13 76 #define EXC_STORE_PAGE_FAULT 15 77 78 /* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */ 79 #define SIE_SSIE (_AC(0x1, UL) << IRQ_S_SOFT) 80 #define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER) 81 #define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT) 82 83 #define CSR_CYCLE 0xc00 84 #define CSR_TIME 0xc01 85 #define CSR_INSTRET 0xc02 86 #define CSR_SSTATUS 0x100 87 #define CSR_SIE 0x104 88 #define CSR_STVEC 0x105 89 #define CSR_SCOUNTEREN 0x106 90 #define CSR_SSCRATCH 0x140 91 #define CSR_SEPC 0x141 92 #define CSR_SCAUSE 0x142 93 #define CSR_STVAL 0x143 94 #define CSR_SIP 0x144 95 #define CSR_SATP 0x180 96 #define CSR_CYCLEH 0xc80 97 #define CSR_TIMEH 0xc81 98 #define CSR_INSTRETH 0xc82 99 100 #ifndef __ASSEMBLY__ 101 102 #define csr_swap(csr, val) \ 103 ({ \ 104 unsigned long __v = (unsigned long)(val); \ 105 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ 106 : "=r" (__v) : "rK" (__v) \ 107 : "memory"); \ 108 __v; \ 109 }) 110 111 #define csr_read(csr) \ 112 ({ \ 113 register unsigned long __v; \ 114 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ 115 : "=r" (__v) : \ 116 : "memory"); \ 117 __v; \ 118 }) 119 120 #define csr_write(csr, val) \ 121 ({ \ 122 unsigned long __v = (unsigned long)(val); \ 123 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ 124 : : "rK" (__v) \ 125 : "memory"); \ 126 }) 127 128 #define csr_read_set(csr, val) \ 129 ({ \ 130 unsigned long __v = (unsigned long)(val); \ 131 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ 132 : "=r" (__v) : "rK" (__v) \ 133 : "memory"); \ 134 __v; \ 135 }) 136 137 #define csr_set(csr, val) \ 138 ({ \ 139 unsigned long __v = (unsigned long)(val); \ 140 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ 141 : : "rK" (__v) \ 142 : "memory"); \ 143 }) 144 145 #define csr_read_clear(csr, val) \ 146 ({ \ 147 unsigned long __v = (unsigned long)(val); \ 148 __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ 149 : "=r" (__v) : "rK" (__v) \ 150 : "memory"); \ 151 __v; \ 152 }) 153 154 #define csr_clear(csr, val) \ 155 ({ \ 156 unsigned long __v = (unsigned long)(val); \ 157 __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ 158 : : "rK" (__v) \ 159 : "memory"); \ 160 }) 161 162 #endif /* __ASSEMBLY__ */ 163 164 #endif /* _ASM_RISCV_CSR_H */ 165