1 /* 2 * Copyright (C) 2015 Regents of the University of California 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation, version 2. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #ifndef _ASM_RISCV_CSR_H 15 #define _ASM_RISCV_CSR_H 16 17 #include <linux/const.h> 18 19 /* Status register flags */ 20 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ 21 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ 22 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ 23 #define SR_SUM _AC(0x00040000, UL) /* Supervisor may access User Memory */ 24 25 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ 26 #define SR_FS_OFF _AC(0x00000000, UL) 27 #define SR_FS_INITIAL _AC(0x00002000, UL) 28 #define SR_FS_CLEAN _AC(0x00004000, UL) 29 #define SR_FS_DIRTY _AC(0x00006000, UL) 30 31 #define SR_XS _AC(0x00018000, UL) /* Extension Status */ 32 #define SR_XS_OFF _AC(0x00000000, UL) 33 #define SR_XS_INITIAL _AC(0x00008000, UL) 34 #define SR_XS_CLEAN _AC(0x00010000, UL) 35 #define SR_XS_DIRTY _AC(0x00018000, UL) 36 37 #ifndef CONFIG_64BIT 38 #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ 39 #else 40 #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ 41 #endif 42 43 /* SATP flags */ 44 #if __riscv_xlen == 32 45 #define SATP_PPN _AC(0x003FFFFF, UL) 46 #define SATP_MODE_32 _AC(0x80000000, UL) 47 #define SATP_MODE SATP_MODE_32 48 #else 49 #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) 50 #define SATP_MODE_39 _AC(0x8000000000000000, UL) 51 #define SATP_MODE SATP_MODE_39 52 #endif 53 54 /* Interrupt Enable and Interrupt Pending flags */ 55 #define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */ 56 #define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */ 57 58 #define EXC_INST_MISALIGNED 0 59 #define EXC_INST_ACCESS 1 60 #define EXC_BREAKPOINT 3 61 #define EXC_LOAD_ACCESS 5 62 #define EXC_STORE_ACCESS 7 63 #define EXC_SYSCALL 8 64 #define EXC_INST_PAGE_FAULT 12 65 #define EXC_LOAD_PAGE_FAULT 13 66 #define EXC_STORE_PAGE_FAULT 15 67 68 #ifndef __ASSEMBLY__ 69 70 #define csr_swap(csr, val) \ 71 ({ \ 72 unsigned long __v = (unsigned long)(val); \ 73 __asm__ __volatile__ ("csrrw %0, " #csr ", %1" \ 74 : "=r" (__v) : "rK" (__v) \ 75 : "memory"); \ 76 __v; \ 77 }) 78 79 #define csr_read(csr) \ 80 ({ \ 81 register unsigned long __v; \ 82 __asm__ __volatile__ ("csrr %0, " #csr \ 83 : "=r" (__v) : \ 84 : "memory"); \ 85 __v; \ 86 }) 87 88 #define csr_write(csr, val) \ 89 ({ \ 90 unsigned long __v = (unsigned long)(val); \ 91 __asm__ __volatile__ ("csrw " #csr ", %0" \ 92 : : "rK" (__v) \ 93 : "memory"); \ 94 }) 95 96 #define csr_read_set(csr, val) \ 97 ({ \ 98 unsigned long __v = (unsigned long)(val); \ 99 __asm__ __volatile__ ("csrrs %0, " #csr ", %1" \ 100 : "=r" (__v) : "rK" (__v) \ 101 : "memory"); \ 102 __v; \ 103 }) 104 105 #define csr_set(csr, val) \ 106 ({ \ 107 unsigned long __v = (unsigned long)(val); \ 108 __asm__ __volatile__ ("csrs " #csr ", %0" \ 109 : : "rK" (__v) \ 110 : "memory"); \ 111 }) 112 113 #define csr_read_clear(csr, val) \ 114 ({ \ 115 unsigned long __v = (unsigned long)(val); \ 116 __asm__ __volatile__ ("csrrc %0, " #csr ", %1" \ 117 : "=r" (__v) : "rK" (__v) \ 118 : "memory"); \ 119 __v; \ 120 }) 121 122 #define csr_clear(csr, val) \ 123 ({ \ 124 unsigned long __v = (unsigned long)(val); \ 125 __asm__ __volatile__ ("csrc " #csr ", %0" \ 126 : : "rK" (__v) \ 127 : "memory"); \ 128 }) 129 130 #endif /* __ASSEMBLY__ */ 131 132 #endif /* _ASM_RISCV_CSR_H */ 133