1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_CSR_H 7 #define _ASM_RISCV_CSR_H 8 9 #include <asm/asm.h> 10 #include <linux/bits.h> 11 12 /* Status register flags */ 13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ 14 #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */ 15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ 16 #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */ 17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ 18 #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ 19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ 20 21 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ 22 #define SR_FS_OFF _AC(0x00000000, UL) 23 #define SR_FS_INITIAL _AC(0x00002000, UL) 24 #define SR_FS_CLEAN _AC(0x00004000, UL) 25 #define SR_FS_DIRTY _AC(0x00006000, UL) 26 27 #define SR_XS _AC(0x00018000, UL) /* Extension Status */ 28 #define SR_XS_OFF _AC(0x00000000, UL) 29 #define SR_XS_INITIAL _AC(0x00008000, UL) 30 #define SR_XS_CLEAN _AC(0x00010000, UL) 31 #define SR_XS_DIRTY _AC(0x00018000, UL) 32 33 #ifndef CONFIG_64BIT 34 #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ 35 #else 36 #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ 37 #endif 38 39 #ifdef CONFIG_64BIT 40 #define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */ 41 #define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */ 42 #define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */ 43 #endif 44 45 /* SATP flags */ 46 #ifndef CONFIG_64BIT 47 #define SATP_PPN _AC(0x003FFFFF, UL) 48 #define SATP_MODE_32 _AC(0x80000000, UL) 49 #define SATP_ASID_BITS 9 50 #define SATP_ASID_SHIFT 22 51 #define SATP_ASID_MASK _AC(0x1FF, UL) 52 #else 53 #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) 54 #define SATP_MODE_39 _AC(0x8000000000000000, UL) 55 #define SATP_MODE_48 _AC(0x9000000000000000, UL) 56 #define SATP_MODE_57 _AC(0xa000000000000000, UL) 57 #define SATP_ASID_BITS 16 58 #define SATP_ASID_SHIFT 44 59 #define SATP_ASID_MASK _AC(0xFFFF, UL) 60 #endif 61 62 /* Exception cause high bit - is an interrupt if set */ 63 #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) 64 65 /* Interrupt causes (minus the high bit) */ 66 #define IRQ_S_SOFT 1 67 #define IRQ_VS_SOFT 2 68 #define IRQ_M_SOFT 3 69 #define IRQ_S_TIMER 5 70 #define IRQ_VS_TIMER 6 71 #define IRQ_M_TIMER 7 72 #define IRQ_S_EXT 9 73 #define IRQ_VS_EXT 10 74 #define IRQ_M_EXT 11 75 #define IRQ_S_GEXT 12 76 #define IRQ_PMU_OVF 13 77 #define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1) 78 #define IRQ_LOCAL_MASK GENMASK((IRQ_LOCAL_MAX - 1), 0) 79 80 /* Exception causes */ 81 #define EXC_INST_MISALIGNED 0 82 #define EXC_INST_ACCESS 1 83 #define EXC_INST_ILLEGAL 2 84 #define EXC_BREAKPOINT 3 85 #define EXC_LOAD_ACCESS 5 86 #define EXC_STORE_ACCESS 7 87 #define EXC_SYSCALL 8 88 #define EXC_HYPERVISOR_SYSCALL 9 89 #define EXC_SUPERVISOR_SYSCALL 10 90 #define EXC_INST_PAGE_FAULT 12 91 #define EXC_LOAD_PAGE_FAULT 13 92 #define EXC_STORE_PAGE_FAULT 15 93 #define EXC_INST_GUEST_PAGE_FAULT 20 94 #define EXC_LOAD_GUEST_PAGE_FAULT 21 95 #define EXC_VIRTUAL_INST_FAULT 22 96 #define EXC_STORE_GUEST_PAGE_FAULT 23 97 98 /* PMP configuration */ 99 #define PMP_R 0x01 100 #define PMP_W 0x02 101 #define PMP_X 0x04 102 #define PMP_A 0x18 103 #define PMP_A_TOR 0x08 104 #define PMP_A_NA4 0x10 105 #define PMP_A_NAPOT 0x18 106 #define PMP_L 0x80 107 108 /* HSTATUS flags */ 109 #ifdef CONFIG_64BIT 110 #define HSTATUS_VSXL _AC(0x300000000, UL) 111 #define HSTATUS_VSXL_SHIFT 32 112 #endif 113 #define HSTATUS_VTSR _AC(0x00400000, UL) 114 #define HSTATUS_VTW _AC(0x00200000, UL) 115 #define HSTATUS_VTVM _AC(0x00100000, UL) 116 #define HSTATUS_VGEIN _AC(0x0003f000, UL) 117 #define HSTATUS_VGEIN_SHIFT 12 118 #define HSTATUS_HU _AC(0x00000200, UL) 119 #define HSTATUS_SPVP _AC(0x00000100, UL) 120 #define HSTATUS_SPV _AC(0x00000080, UL) 121 #define HSTATUS_GVA _AC(0x00000040, UL) 122 #define HSTATUS_VSBE _AC(0x00000020, UL) 123 124 /* HGATP flags */ 125 #define HGATP_MODE_OFF _AC(0, UL) 126 #define HGATP_MODE_SV32X4 _AC(1, UL) 127 #define HGATP_MODE_SV39X4 _AC(8, UL) 128 #define HGATP_MODE_SV48X4 _AC(9, UL) 129 #define HGATP_MODE_SV57X4 _AC(10, UL) 130 131 #define HGATP32_MODE_SHIFT 31 132 #define HGATP32_VMID_SHIFT 22 133 #define HGATP32_VMID GENMASK(28, 22) 134 #define HGATP32_PPN GENMASK(21, 0) 135 136 #define HGATP64_MODE_SHIFT 60 137 #define HGATP64_VMID_SHIFT 44 138 #define HGATP64_VMID GENMASK(57, 44) 139 #define HGATP64_PPN GENMASK(43, 0) 140 141 #define HGATP_PAGE_SHIFT 12 142 143 #ifdef CONFIG_64BIT 144 #define HGATP_PPN HGATP64_PPN 145 #define HGATP_VMID_SHIFT HGATP64_VMID_SHIFT 146 #define HGATP_VMID HGATP64_VMID 147 #define HGATP_MODE_SHIFT HGATP64_MODE_SHIFT 148 #else 149 #define HGATP_PPN HGATP32_PPN 150 #define HGATP_VMID_SHIFT HGATP32_VMID_SHIFT 151 #define HGATP_VMID HGATP32_VMID 152 #define HGATP_MODE_SHIFT HGATP32_MODE_SHIFT 153 #endif 154 155 /* VSIP & HVIP relation */ 156 #define VSIP_TO_HVIP_SHIFT (IRQ_VS_SOFT - IRQ_S_SOFT) 157 #define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \ 158 (_AC(1, UL) << IRQ_S_TIMER) | \ 159 (_AC(1, UL) << IRQ_S_EXT)) 160 161 /* AIA CSR bits */ 162 #define TOPI_IID_SHIFT 16 163 #define TOPI_IID_MASK GENMASK(11, 0) 164 #define TOPI_IPRIO_MASK GENMASK(7, 0) 165 #define TOPI_IPRIO_BITS 8 166 167 #define TOPEI_ID_SHIFT 16 168 #define TOPEI_ID_MASK GENMASK(10, 0) 169 #define TOPEI_PRIO_MASK GENMASK(10, 0) 170 171 #define ISELECT_IPRIO0 0x30 172 #define ISELECT_IPRIO15 0x3f 173 #define ISELECT_MASK GENMASK(8, 0) 174 175 #define HVICTL_VTI BIT(30) 176 #define HVICTL_IID GENMASK(27, 16) 177 #define HVICTL_IID_SHIFT 16 178 #define HVICTL_DPR BIT(9) 179 #define HVICTL_IPRIOM BIT(8) 180 #define HVICTL_IPRIO GENMASK(7, 0) 181 182 /* xENVCFG flags */ 183 #define ENVCFG_STCE (_AC(1, ULL) << 63) 184 #define ENVCFG_PBMTE (_AC(1, ULL) << 62) 185 #define ENVCFG_CBZE (_AC(1, UL) << 7) 186 #define ENVCFG_CBCFE (_AC(1, UL) << 6) 187 #define ENVCFG_CBIE_SHIFT 4 188 #define ENVCFG_CBIE (_AC(0x3, UL) << ENVCFG_CBIE_SHIFT) 189 #define ENVCFG_CBIE_ILL _AC(0x0, UL) 190 #define ENVCFG_CBIE_FLUSH _AC(0x1, UL) 191 #define ENVCFG_CBIE_INV _AC(0x3, UL) 192 #define ENVCFG_FIOM _AC(0x1, UL) 193 194 /* symbolic CSR names: */ 195 #define CSR_CYCLE 0xc00 196 #define CSR_TIME 0xc01 197 #define CSR_INSTRET 0xc02 198 #define CSR_HPMCOUNTER3 0xc03 199 #define CSR_HPMCOUNTER4 0xc04 200 #define CSR_HPMCOUNTER5 0xc05 201 #define CSR_HPMCOUNTER6 0xc06 202 #define CSR_HPMCOUNTER7 0xc07 203 #define CSR_HPMCOUNTER8 0xc08 204 #define CSR_HPMCOUNTER9 0xc09 205 #define CSR_HPMCOUNTER10 0xc0a 206 #define CSR_HPMCOUNTER11 0xc0b 207 #define CSR_HPMCOUNTER12 0xc0c 208 #define CSR_HPMCOUNTER13 0xc0d 209 #define CSR_HPMCOUNTER14 0xc0e 210 #define CSR_HPMCOUNTER15 0xc0f 211 #define CSR_HPMCOUNTER16 0xc10 212 #define CSR_HPMCOUNTER17 0xc11 213 #define CSR_HPMCOUNTER18 0xc12 214 #define CSR_HPMCOUNTER19 0xc13 215 #define CSR_HPMCOUNTER20 0xc14 216 #define CSR_HPMCOUNTER21 0xc15 217 #define CSR_HPMCOUNTER22 0xc16 218 #define CSR_HPMCOUNTER23 0xc17 219 #define CSR_HPMCOUNTER24 0xc18 220 #define CSR_HPMCOUNTER25 0xc19 221 #define CSR_HPMCOUNTER26 0xc1a 222 #define CSR_HPMCOUNTER27 0xc1b 223 #define CSR_HPMCOUNTER28 0xc1c 224 #define CSR_HPMCOUNTER29 0xc1d 225 #define CSR_HPMCOUNTER30 0xc1e 226 #define CSR_HPMCOUNTER31 0xc1f 227 #define CSR_CYCLEH 0xc80 228 #define CSR_TIMEH 0xc81 229 #define CSR_INSTRETH 0xc82 230 #define CSR_HPMCOUNTER3H 0xc83 231 #define CSR_HPMCOUNTER4H 0xc84 232 #define CSR_HPMCOUNTER5H 0xc85 233 #define CSR_HPMCOUNTER6H 0xc86 234 #define CSR_HPMCOUNTER7H 0xc87 235 #define CSR_HPMCOUNTER8H 0xc88 236 #define CSR_HPMCOUNTER9H 0xc89 237 #define CSR_HPMCOUNTER10H 0xc8a 238 #define CSR_HPMCOUNTER11H 0xc8b 239 #define CSR_HPMCOUNTER12H 0xc8c 240 #define CSR_HPMCOUNTER13H 0xc8d 241 #define CSR_HPMCOUNTER14H 0xc8e 242 #define CSR_HPMCOUNTER15H 0xc8f 243 #define CSR_HPMCOUNTER16H 0xc90 244 #define CSR_HPMCOUNTER17H 0xc91 245 #define CSR_HPMCOUNTER18H 0xc92 246 #define CSR_HPMCOUNTER19H 0xc93 247 #define CSR_HPMCOUNTER20H 0xc94 248 #define CSR_HPMCOUNTER21H 0xc95 249 #define CSR_HPMCOUNTER22H 0xc96 250 #define CSR_HPMCOUNTER23H 0xc97 251 #define CSR_HPMCOUNTER24H 0xc98 252 #define CSR_HPMCOUNTER25H 0xc99 253 #define CSR_HPMCOUNTER26H 0xc9a 254 #define CSR_HPMCOUNTER27H 0xc9b 255 #define CSR_HPMCOUNTER28H 0xc9c 256 #define CSR_HPMCOUNTER29H 0xc9d 257 #define CSR_HPMCOUNTER30H 0xc9e 258 #define CSR_HPMCOUNTER31H 0xc9f 259 260 #define CSR_SSCOUNTOVF 0xda0 261 262 #define CSR_SSTATUS 0x100 263 #define CSR_SIE 0x104 264 #define CSR_STVEC 0x105 265 #define CSR_SCOUNTEREN 0x106 266 #define CSR_SSCRATCH 0x140 267 #define CSR_SEPC 0x141 268 #define CSR_SCAUSE 0x142 269 #define CSR_STVAL 0x143 270 #define CSR_SIP 0x144 271 #define CSR_SATP 0x180 272 273 #define CSR_STIMECMP 0x14D 274 #define CSR_STIMECMPH 0x15D 275 276 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ 277 #define CSR_SISELECT 0x150 278 #define CSR_SIREG 0x151 279 280 /* Supervisor-Level Interrupts (AIA) */ 281 #define CSR_STOPEI 0x15c 282 #define CSR_STOPI 0xdb0 283 284 /* Supervisor-Level High-Half CSRs (AIA) */ 285 #define CSR_SIEH 0x114 286 #define CSR_SIPH 0x154 287 288 #define CSR_VSSTATUS 0x200 289 #define CSR_VSIE 0x204 290 #define CSR_VSTVEC 0x205 291 #define CSR_VSSCRATCH 0x240 292 #define CSR_VSEPC 0x241 293 #define CSR_VSCAUSE 0x242 294 #define CSR_VSTVAL 0x243 295 #define CSR_VSIP 0x244 296 #define CSR_VSATP 0x280 297 #define CSR_VSTIMECMP 0x24D 298 #define CSR_VSTIMECMPH 0x25D 299 300 #define CSR_HSTATUS 0x600 301 #define CSR_HEDELEG 0x602 302 #define CSR_HIDELEG 0x603 303 #define CSR_HIE 0x604 304 #define CSR_HTIMEDELTA 0x605 305 #define CSR_HCOUNTEREN 0x606 306 #define CSR_HGEIE 0x607 307 #define CSR_HENVCFG 0x60a 308 #define CSR_HTIMEDELTAH 0x615 309 #define CSR_HENVCFGH 0x61a 310 #define CSR_HTVAL 0x643 311 #define CSR_HIP 0x644 312 #define CSR_HVIP 0x645 313 #define CSR_HTINST 0x64a 314 #define CSR_HGATP 0x680 315 #define CSR_HGEIP 0xe12 316 317 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ 318 #define CSR_HVIEN 0x608 319 #define CSR_HVICTL 0x609 320 #define CSR_HVIPRIO1 0x646 321 #define CSR_HVIPRIO2 0x647 322 323 /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */ 324 #define CSR_VSISELECT 0x250 325 #define CSR_VSIREG 0x251 326 327 /* VS-Level Interrupts (H-extension with AIA) */ 328 #define CSR_VSTOPEI 0x25c 329 #define CSR_VSTOPI 0xeb0 330 331 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ 332 #define CSR_HIDELEGH 0x613 333 #define CSR_HVIENH 0x618 334 #define CSR_HVIPH 0x655 335 #define CSR_HVIPRIO1H 0x656 336 #define CSR_HVIPRIO2H 0x657 337 #define CSR_VSIEH 0x214 338 #define CSR_VSIPH 0x254 339 340 #define CSR_MSTATUS 0x300 341 #define CSR_MISA 0x301 342 #define CSR_MIDELEG 0x303 343 #define CSR_MIE 0x304 344 #define CSR_MTVEC 0x305 345 #define CSR_MENVCFG 0x30a 346 #define CSR_MENVCFGH 0x31a 347 #define CSR_MSCRATCH 0x340 348 #define CSR_MEPC 0x341 349 #define CSR_MCAUSE 0x342 350 #define CSR_MTVAL 0x343 351 #define CSR_MIP 0x344 352 #define CSR_PMPCFG0 0x3a0 353 #define CSR_PMPADDR0 0x3b0 354 #define CSR_MVENDORID 0xf11 355 #define CSR_MARCHID 0xf12 356 #define CSR_MIMPID 0xf13 357 #define CSR_MHARTID 0xf14 358 359 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ 360 #define CSR_MISELECT 0x350 361 #define CSR_MIREG 0x351 362 363 /* Machine-Level Interrupts (AIA) */ 364 #define CSR_MTOPEI 0x35c 365 #define CSR_MTOPI 0xfb0 366 367 /* Virtual Interrupts for Supervisor Level (AIA) */ 368 #define CSR_MVIEN 0x308 369 #define CSR_MVIP 0x309 370 371 /* Machine-Level High-Half CSRs (AIA) */ 372 #define CSR_MIDELEGH 0x313 373 #define CSR_MIEH 0x314 374 #define CSR_MVIENH 0x318 375 #define CSR_MVIPH 0x319 376 #define CSR_MIPH 0x354 377 378 #ifdef CONFIG_RISCV_M_MODE 379 # define CSR_STATUS CSR_MSTATUS 380 # define CSR_IE CSR_MIE 381 # define CSR_TVEC CSR_MTVEC 382 # define CSR_SCRATCH CSR_MSCRATCH 383 # define CSR_EPC CSR_MEPC 384 # define CSR_CAUSE CSR_MCAUSE 385 # define CSR_TVAL CSR_MTVAL 386 # define CSR_IP CSR_MIP 387 388 # define CSR_IEH CSR_MIEH 389 # define CSR_ISELECT CSR_MISELECT 390 # define CSR_IREG CSR_MIREG 391 # define CSR_IPH CSR_MIPH 392 # define CSR_TOPEI CSR_MTOPEI 393 # define CSR_TOPI CSR_MTOPI 394 395 # define SR_IE SR_MIE 396 # define SR_PIE SR_MPIE 397 # define SR_PP SR_MPP 398 399 # define RV_IRQ_SOFT IRQ_M_SOFT 400 # define RV_IRQ_TIMER IRQ_M_TIMER 401 # define RV_IRQ_EXT IRQ_M_EXT 402 #else /* CONFIG_RISCV_M_MODE */ 403 # define CSR_STATUS CSR_SSTATUS 404 # define CSR_IE CSR_SIE 405 # define CSR_TVEC CSR_STVEC 406 # define CSR_SCRATCH CSR_SSCRATCH 407 # define CSR_EPC CSR_SEPC 408 # define CSR_CAUSE CSR_SCAUSE 409 # define CSR_TVAL CSR_STVAL 410 # define CSR_IP CSR_SIP 411 412 # define CSR_IEH CSR_SIEH 413 # define CSR_ISELECT CSR_SISELECT 414 # define CSR_IREG CSR_SIREG 415 # define CSR_IPH CSR_SIPH 416 # define CSR_TOPEI CSR_STOPEI 417 # define CSR_TOPI CSR_STOPI 418 419 # define SR_IE SR_SIE 420 # define SR_PIE SR_SPIE 421 # define SR_PP SR_SPP 422 423 # define RV_IRQ_SOFT IRQ_S_SOFT 424 # define RV_IRQ_TIMER IRQ_S_TIMER 425 # define RV_IRQ_EXT IRQ_S_EXT 426 # define RV_IRQ_PMU IRQ_PMU_OVF 427 # define SIP_LCOFIP (_AC(0x1, UL) << IRQ_PMU_OVF) 428 429 #endif /* !CONFIG_RISCV_M_MODE */ 430 431 /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */ 432 #define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT) 433 #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER) 434 #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT) 435 436 #ifndef __ASSEMBLY__ 437 438 #define csr_swap(csr, val) \ 439 ({ \ 440 unsigned long __v = (unsigned long)(val); \ 441 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ 442 : "=r" (__v) : "rK" (__v) \ 443 : "memory"); \ 444 __v; \ 445 }) 446 447 #define csr_read(csr) \ 448 ({ \ 449 register unsigned long __v; \ 450 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ 451 : "=r" (__v) : \ 452 : "memory"); \ 453 __v; \ 454 }) 455 456 #define csr_write(csr, val) \ 457 ({ \ 458 unsigned long __v = (unsigned long)(val); \ 459 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ 460 : : "rK" (__v) \ 461 : "memory"); \ 462 }) 463 464 #define csr_read_set(csr, val) \ 465 ({ \ 466 unsigned long __v = (unsigned long)(val); \ 467 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ 468 : "=r" (__v) : "rK" (__v) \ 469 : "memory"); \ 470 __v; \ 471 }) 472 473 #define csr_set(csr, val) \ 474 ({ \ 475 unsigned long __v = (unsigned long)(val); \ 476 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ 477 : : "rK" (__v) \ 478 : "memory"); \ 479 }) 480 481 #define csr_read_clear(csr, val) \ 482 ({ \ 483 unsigned long __v = (unsigned long)(val); \ 484 __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ 485 : "=r" (__v) : "rK" (__v) \ 486 : "memory"); \ 487 __v; \ 488 }) 489 490 #define csr_clear(csr, val) \ 491 ({ \ 492 unsigned long __v = (unsigned long)(val); \ 493 __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ 494 : : "rK" (__v) \ 495 : "memory"); \ 496 }) 497 498 #endif /* __ASSEMBLY__ */ 499 500 #endif /* _ASM_RISCV_CSR_H */ 501