1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_CSR_H 7 #define _ASM_RISCV_CSR_H 8 9 #include <asm/asm.h> 10 #include <linux/const.h> 11 12 /* Status register flags */ 13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ 14 #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */ 15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ 16 #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */ 17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ 18 #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ 19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ 20 21 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ 22 #define SR_FS_OFF _AC(0x00000000, UL) 23 #define SR_FS_INITIAL _AC(0x00002000, UL) 24 #define SR_FS_CLEAN _AC(0x00004000, UL) 25 #define SR_FS_DIRTY _AC(0x00006000, UL) 26 27 #define SR_XS _AC(0x00018000, UL) /* Extension Status */ 28 #define SR_XS_OFF _AC(0x00000000, UL) 29 #define SR_XS_INITIAL _AC(0x00008000, UL) 30 #define SR_XS_CLEAN _AC(0x00010000, UL) 31 #define SR_XS_DIRTY _AC(0x00018000, UL) 32 33 #ifndef CONFIG_64BIT 34 #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ 35 #else 36 #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ 37 #endif 38 39 /* SATP flags */ 40 #ifndef CONFIG_64BIT 41 #define SATP_PPN _AC(0x003FFFFF, UL) 42 #define SATP_MODE_32 _AC(0x80000000, UL) 43 #define SATP_MODE SATP_MODE_32 44 #define SATP_ASID_BITS 9 45 #define SATP_ASID_SHIFT 22 46 #define SATP_ASID_MASK _AC(0x1FF, UL) 47 #else 48 #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) 49 #define SATP_MODE_39 _AC(0x8000000000000000, UL) 50 #define SATP_MODE SATP_MODE_39 51 #define SATP_ASID_BITS 16 52 #define SATP_ASID_SHIFT 44 53 #define SATP_ASID_MASK _AC(0xFFFF, UL) 54 #endif 55 56 /* Exception cause high bit - is an interrupt if set */ 57 #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) 58 59 /* Interrupt causes (minus the high bit) */ 60 #define IRQ_S_SOFT 1 61 #define IRQ_M_SOFT 3 62 #define IRQ_S_TIMER 5 63 #define IRQ_M_TIMER 7 64 #define IRQ_S_EXT 9 65 #define IRQ_M_EXT 11 66 67 /* Exception causes */ 68 #define EXC_INST_MISALIGNED 0 69 #define EXC_INST_ACCESS 1 70 #define EXC_BREAKPOINT 3 71 #define EXC_LOAD_ACCESS 5 72 #define EXC_STORE_ACCESS 7 73 #define EXC_SYSCALL 8 74 #define EXC_INST_PAGE_FAULT 12 75 #define EXC_LOAD_PAGE_FAULT 13 76 #define EXC_STORE_PAGE_FAULT 15 77 78 /* PMP configuration */ 79 #define PMP_R 0x01 80 #define PMP_W 0x02 81 #define PMP_X 0x04 82 #define PMP_A 0x18 83 #define PMP_A_TOR 0x08 84 #define PMP_A_NA4 0x10 85 #define PMP_A_NAPOT 0x18 86 #define PMP_L 0x80 87 88 /* symbolic CSR names: */ 89 #define CSR_CYCLE 0xc00 90 #define CSR_TIME 0xc01 91 #define CSR_INSTRET 0xc02 92 #define CSR_CYCLEH 0xc80 93 #define CSR_TIMEH 0xc81 94 #define CSR_INSTRETH 0xc82 95 96 #define CSR_SSTATUS 0x100 97 #define CSR_SIE 0x104 98 #define CSR_STVEC 0x105 99 #define CSR_SCOUNTEREN 0x106 100 #define CSR_SSCRATCH 0x140 101 #define CSR_SEPC 0x141 102 #define CSR_SCAUSE 0x142 103 #define CSR_STVAL 0x143 104 #define CSR_SIP 0x144 105 #define CSR_SATP 0x180 106 107 #define CSR_MSTATUS 0x300 108 #define CSR_MISA 0x301 109 #define CSR_MIE 0x304 110 #define CSR_MTVEC 0x305 111 #define CSR_MSCRATCH 0x340 112 #define CSR_MEPC 0x341 113 #define CSR_MCAUSE 0x342 114 #define CSR_MTVAL 0x343 115 #define CSR_MIP 0x344 116 #define CSR_PMPCFG0 0x3a0 117 #define CSR_PMPADDR0 0x3b0 118 #define CSR_MHARTID 0xf14 119 120 #ifdef CONFIG_RISCV_M_MODE 121 # define CSR_STATUS CSR_MSTATUS 122 # define CSR_IE CSR_MIE 123 # define CSR_TVEC CSR_MTVEC 124 # define CSR_SCRATCH CSR_MSCRATCH 125 # define CSR_EPC CSR_MEPC 126 # define CSR_CAUSE CSR_MCAUSE 127 # define CSR_TVAL CSR_MTVAL 128 # define CSR_IP CSR_MIP 129 130 # define SR_IE SR_MIE 131 # define SR_PIE SR_MPIE 132 # define SR_PP SR_MPP 133 134 # define RV_IRQ_SOFT IRQ_M_SOFT 135 # define RV_IRQ_TIMER IRQ_M_TIMER 136 # define RV_IRQ_EXT IRQ_M_EXT 137 #else /* CONFIG_RISCV_M_MODE */ 138 # define CSR_STATUS CSR_SSTATUS 139 # define CSR_IE CSR_SIE 140 # define CSR_TVEC CSR_STVEC 141 # define CSR_SCRATCH CSR_SSCRATCH 142 # define CSR_EPC CSR_SEPC 143 # define CSR_CAUSE CSR_SCAUSE 144 # define CSR_TVAL CSR_STVAL 145 # define CSR_IP CSR_SIP 146 147 # define SR_IE SR_SIE 148 # define SR_PIE SR_SPIE 149 # define SR_PP SR_SPP 150 151 # define RV_IRQ_SOFT IRQ_S_SOFT 152 # define RV_IRQ_TIMER IRQ_S_TIMER 153 # define RV_IRQ_EXT IRQ_S_EXT 154 #endif /* CONFIG_RISCV_M_MODE */ 155 156 /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */ 157 #define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT) 158 #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER) 159 #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT) 160 161 #ifndef __ASSEMBLY__ 162 163 #define csr_swap(csr, val) \ 164 ({ \ 165 unsigned long __v = (unsigned long)(val); \ 166 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ 167 : "=r" (__v) : "rK" (__v) \ 168 : "memory"); \ 169 __v; \ 170 }) 171 172 #define csr_read(csr) \ 173 ({ \ 174 register unsigned long __v; \ 175 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ 176 : "=r" (__v) : \ 177 : "memory"); \ 178 __v; \ 179 }) 180 181 #define csr_write(csr, val) \ 182 ({ \ 183 unsigned long __v = (unsigned long)(val); \ 184 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ 185 : : "rK" (__v) \ 186 : "memory"); \ 187 }) 188 189 #define csr_read_set(csr, val) \ 190 ({ \ 191 unsigned long __v = (unsigned long)(val); \ 192 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ 193 : "=r" (__v) : "rK" (__v) \ 194 : "memory"); \ 195 __v; \ 196 }) 197 198 #define csr_set(csr, val) \ 199 ({ \ 200 unsigned long __v = (unsigned long)(val); \ 201 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ 202 : : "rK" (__v) \ 203 : "memory"); \ 204 }) 205 206 #define csr_read_clear(csr, val) \ 207 ({ \ 208 unsigned long __v = (unsigned long)(val); \ 209 __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ 210 : "=r" (__v) : "rK" (__v) \ 211 : "memory"); \ 212 __v; \ 213 }) 214 215 #define csr_clear(csr, val) \ 216 ({ \ 217 unsigned long __v = (unsigned long)(val); \ 218 __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ 219 : : "rK" (__v) \ 220 : "memory"); \ 221 }) 222 223 #endif /* __ASSEMBLY__ */ 224 225 #endif /* _ASM_RISCV_CSR_H */ 226