xref: /openbmc/linux/arch/riscv/include/asm/csr.h (revision 228662b0)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2015 Regents of the University of California
4  */
5 
6 #ifndef _ASM_RISCV_CSR_H
7 #define _ASM_RISCV_CSR_H
8 
9 #include <asm/asm.h>
10 #include <linux/const.h>
11 
12 /* Status register flags */
13 #define SR_SIE		_AC(0x00000002, UL) /* Supervisor Interrupt Enable */
14 #define SR_MIE		_AC(0x00000008, UL) /* Machine Interrupt Enable */
15 #define SR_SPIE		_AC(0x00000020, UL) /* Previous Supervisor IE */
16 #define SR_MPIE		_AC(0x00000080, UL) /* Previous Machine IE */
17 #define SR_SPP		_AC(0x00000100, UL) /* Previously Supervisor */
18 #define SR_MPP		_AC(0x00001800, UL) /* Previously Machine */
19 #define SR_SUM		_AC(0x00040000, UL) /* Supervisor User Memory Access */
20 
21 #define SR_FS		_AC(0x00006000, UL) /* Floating-point Status */
22 #define SR_FS_OFF	_AC(0x00000000, UL)
23 #define SR_FS_INITIAL	_AC(0x00002000, UL)
24 #define SR_FS_CLEAN	_AC(0x00004000, UL)
25 #define SR_FS_DIRTY	_AC(0x00006000, UL)
26 
27 #define SR_XS		_AC(0x00018000, UL) /* Extension Status */
28 #define SR_XS_OFF	_AC(0x00000000, UL)
29 #define SR_XS_INITIAL	_AC(0x00008000, UL)
30 #define SR_XS_CLEAN	_AC(0x00010000, UL)
31 #define SR_XS_DIRTY	_AC(0x00018000, UL)
32 
33 #ifndef CONFIG_64BIT
34 #define SR_SD		_AC(0x80000000, UL) /* FS/XS dirty */
35 #else
36 #define SR_SD		_AC(0x8000000000000000, UL) /* FS/XS dirty */
37 #endif
38 
39 /* SATP flags */
40 #ifndef CONFIG_64BIT
41 #define SATP_PPN	_AC(0x003FFFFF, UL)
42 #define SATP_MODE_32	_AC(0x80000000, UL)
43 #define SATP_ASID_BITS	9
44 #define SATP_ASID_SHIFT	22
45 #define SATP_ASID_MASK	_AC(0x1FF, UL)
46 #else
47 #define SATP_PPN	_AC(0x00000FFFFFFFFFFF, UL)
48 #define SATP_MODE_39	_AC(0x8000000000000000, UL)
49 #define SATP_MODE_48	_AC(0x9000000000000000, UL)
50 #define SATP_MODE_57	_AC(0xa000000000000000, UL)
51 #define SATP_ASID_BITS	16
52 #define SATP_ASID_SHIFT	44
53 #define SATP_ASID_MASK	_AC(0xFFFF, UL)
54 #endif
55 
56 /* Exception cause high bit - is an interrupt if set */
57 #define CAUSE_IRQ_FLAG		(_AC(1, UL) << (__riscv_xlen - 1))
58 
59 /* Interrupt causes (minus the high bit) */
60 #define IRQ_S_SOFT		1
61 #define IRQ_VS_SOFT		2
62 #define IRQ_M_SOFT		3
63 #define IRQ_S_TIMER		5
64 #define IRQ_VS_TIMER		6
65 #define IRQ_M_TIMER		7
66 #define IRQ_S_EXT		9
67 #define IRQ_VS_EXT		10
68 #define IRQ_M_EXT		11
69 #define IRQ_PMU_OVF		13
70 
71 /* Exception causes */
72 #define EXC_INST_MISALIGNED	0
73 #define EXC_INST_ACCESS		1
74 #define EXC_INST_ILLEGAL	2
75 #define EXC_BREAKPOINT		3
76 #define EXC_LOAD_ACCESS		5
77 #define EXC_STORE_ACCESS	7
78 #define EXC_SYSCALL		8
79 #define EXC_HYPERVISOR_SYSCALL	9
80 #define EXC_SUPERVISOR_SYSCALL	10
81 #define EXC_INST_PAGE_FAULT	12
82 #define EXC_LOAD_PAGE_FAULT	13
83 #define EXC_STORE_PAGE_FAULT	15
84 #define EXC_INST_GUEST_PAGE_FAULT	20
85 #define EXC_LOAD_GUEST_PAGE_FAULT	21
86 #define EXC_VIRTUAL_INST_FAULT		22
87 #define EXC_STORE_GUEST_PAGE_FAULT	23
88 
89 /* PMP configuration */
90 #define PMP_R			0x01
91 #define PMP_W			0x02
92 #define PMP_X			0x04
93 #define PMP_A			0x18
94 #define PMP_A_TOR		0x08
95 #define PMP_A_NA4		0x10
96 #define PMP_A_NAPOT		0x18
97 #define PMP_L			0x80
98 
99 /* HSTATUS flags */
100 #ifdef CONFIG_64BIT
101 #define HSTATUS_VSXL		_AC(0x300000000, UL)
102 #define HSTATUS_VSXL_SHIFT	32
103 #endif
104 #define HSTATUS_VTSR		_AC(0x00400000, UL)
105 #define HSTATUS_VTW		_AC(0x00200000, UL)
106 #define HSTATUS_VTVM		_AC(0x00100000, UL)
107 #define HSTATUS_VGEIN		_AC(0x0003f000, UL)
108 #define HSTATUS_VGEIN_SHIFT	12
109 #define HSTATUS_HU		_AC(0x00000200, UL)
110 #define HSTATUS_SPVP		_AC(0x00000100, UL)
111 #define HSTATUS_SPV		_AC(0x00000080, UL)
112 #define HSTATUS_GVA		_AC(0x00000040, UL)
113 #define HSTATUS_VSBE		_AC(0x00000020, UL)
114 
115 /* HGATP flags */
116 #define HGATP_MODE_OFF		_AC(0, UL)
117 #define HGATP_MODE_SV32X4	_AC(1, UL)
118 #define HGATP_MODE_SV39X4	_AC(8, UL)
119 #define HGATP_MODE_SV48X4	_AC(9, UL)
120 
121 #define HGATP32_MODE_SHIFT	31
122 #define HGATP32_VMID_SHIFT	22
123 #define HGATP32_VMID_MASK	_AC(0x1FC00000, UL)
124 #define HGATP32_PPN		_AC(0x003FFFFF, UL)
125 
126 #define HGATP64_MODE_SHIFT	60
127 #define HGATP64_VMID_SHIFT	44
128 #define HGATP64_VMID_MASK	_AC(0x03FFF00000000000, UL)
129 #define HGATP64_PPN		_AC(0x00000FFFFFFFFFFF, UL)
130 
131 #define HGATP_PAGE_SHIFT	12
132 
133 #ifdef CONFIG_64BIT
134 #define HGATP_PPN		HGATP64_PPN
135 #define HGATP_VMID_SHIFT	HGATP64_VMID_SHIFT
136 #define HGATP_VMID_MASK		HGATP64_VMID_MASK
137 #define HGATP_MODE_SHIFT	HGATP64_MODE_SHIFT
138 #else
139 #define HGATP_PPN		HGATP32_PPN
140 #define HGATP_VMID_SHIFT	HGATP32_VMID_SHIFT
141 #define HGATP_VMID_MASK		HGATP32_VMID_MASK
142 #define HGATP_MODE_SHIFT	HGATP32_MODE_SHIFT
143 #endif
144 
145 /* VSIP & HVIP relation */
146 #define VSIP_TO_HVIP_SHIFT	(IRQ_VS_SOFT - IRQ_S_SOFT)
147 #define VSIP_VALID_MASK		((_AC(1, UL) << IRQ_S_SOFT) | \
148 				 (_AC(1, UL) << IRQ_S_TIMER) | \
149 				 (_AC(1, UL) << IRQ_S_EXT))
150 
151 /* symbolic CSR names: */
152 #define CSR_CYCLE		0xc00
153 #define CSR_TIME		0xc01
154 #define CSR_INSTRET		0xc02
155 #define CSR_HPMCOUNTER3		0xc03
156 #define CSR_HPMCOUNTER4		0xc04
157 #define CSR_HPMCOUNTER5		0xc05
158 #define CSR_HPMCOUNTER6		0xc06
159 #define CSR_HPMCOUNTER7		0xc07
160 #define CSR_HPMCOUNTER8		0xc08
161 #define CSR_HPMCOUNTER9		0xc09
162 #define CSR_HPMCOUNTER10	0xc0a
163 #define CSR_HPMCOUNTER11	0xc0b
164 #define CSR_HPMCOUNTER12	0xc0c
165 #define CSR_HPMCOUNTER13	0xc0d
166 #define CSR_HPMCOUNTER14	0xc0e
167 #define CSR_HPMCOUNTER15	0xc0f
168 #define CSR_HPMCOUNTER16	0xc10
169 #define CSR_HPMCOUNTER17	0xc11
170 #define CSR_HPMCOUNTER18	0xc12
171 #define CSR_HPMCOUNTER19	0xc13
172 #define CSR_HPMCOUNTER20	0xc14
173 #define CSR_HPMCOUNTER21	0xc15
174 #define CSR_HPMCOUNTER22	0xc16
175 #define CSR_HPMCOUNTER23	0xc17
176 #define CSR_HPMCOUNTER24	0xc18
177 #define CSR_HPMCOUNTER25	0xc19
178 #define CSR_HPMCOUNTER26	0xc1a
179 #define CSR_HPMCOUNTER27	0xc1b
180 #define CSR_HPMCOUNTER28	0xc1c
181 #define CSR_HPMCOUNTER29	0xc1d
182 #define CSR_HPMCOUNTER30	0xc1e
183 #define CSR_HPMCOUNTER31	0xc1f
184 #define CSR_CYCLEH		0xc80
185 #define CSR_TIMEH		0xc81
186 #define CSR_INSTRETH		0xc82
187 #define CSR_HPMCOUNTER3H	0xc83
188 #define CSR_HPMCOUNTER4H	0xc84
189 #define CSR_HPMCOUNTER5H	0xc85
190 #define CSR_HPMCOUNTER6H	0xc86
191 #define CSR_HPMCOUNTER7H	0xc87
192 #define CSR_HPMCOUNTER8H	0xc88
193 #define CSR_HPMCOUNTER9H	0xc89
194 #define CSR_HPMCOUNTER10H	0xc8a
195 #define CSR_HPMCOUNTER11H	0xc8b
196 #define CSR_HPMCOUNTER12H	0xc8c
197 #define CSR_HPMCOUNTER13H	0xc8d
198 #define CSR_HPMCOUNTER14H	0xc8e
199 #define CSR_HPMCOUNTER15H	0xc8f
200 #define CSR_HPMCOUNTER16H	0xc90
201 #define CSR_HPMCOUNTER17H	0xc91
202 #define CSR_HPMCOUNTER18H	0xc92
203 #define CSR_HPMCOUNTER19H	0xc93
204 #define CSR_HPMCOUNTER20H	0xc94
205 #define CSR_HPMCOUNTER21H	0xc95
206 #define CSR_HPMCOUNTER22H	0xc96
207 #define CSR_HPMCOUNTER23H	0xc97
208 #define CSR_HPMCOUNTER24H	0xc98
209 #define CSR_HPMCOUNTER25H	0xc99
210 #define CSR_HPMCOUNTER26H	0xc9a
211 #define CSR_HPMCOUNTER27H	0xc9b
212 #define CSR_HPMCOUNTER28H	0xc9c
213 #define CSR_HPMCOUNTER29H	0xc9d
214 #define CSR_HPMCOUNTER30H	0xc9e
215 #define CSR_HPMCOUNTER31H	0xc9f
216 
217 #define CSR_SSCOUNTOVF		0xda0
218 
219 #define CSR_SSTATUS		0x100
220 #define CSR_SIE			0x104
221 #define CSR_STVEC		0x105
222 #define CSR_SCOUNTEREN		0x106
223 #define CSR_SSCRATCH		0x140
224 #define CSR_SEPC		0x141
225 #define CSR_SCAUSE		0x142
226 #define CSR_STVAL		0x143
227 #define CSR_SIP			0x144
228 #define CSR_SATP		0x180
229 
230 #define CSR_VSSTATUS		0x200
231 #define CSR_VSIE		0x204
232 #define CSR_VSTVEC		0x205
233 #define CSR_VSSCRATCH		0x240
234 #define CSR_VSEPC		0x241
235 #define CSR_VSCAUSE		0x242
236 #define CSR_VSTVAL		0x243
237 #define CSR_VSIP		0x244
238 #define CSR_VSATP		0x280
239 
240 #define CSR_HSTATUS		0x600
241 #define CSR_HEDELEG		0x602
242 #define CSR_HIDELEG		0x603
243 #define CSR_HIE			0x604
244 #define CSR_HTIMEDELTA		0x605
245 #define CSR_HCOUNTEREN		0x606
246 #define CSR_HGEIE		0x607
247 #define CSR_HTIMEDELTAH		0x615
248 #define CSR_HTVAL		0x643
249 #define CSR_HIP			0x644
250 #define CSR_HVIP		0x645
251 #define CSR_HTINST		0x64a
252 #define CSR_HGATP		0x680
253 #define CSR_HGEIP		0xe12
254 
255 #define CSR_MSTATUS		0x300
256 #define CSR_MISA		0x301
257 #define CSR_MIE			0x304
258 #define CSR_MTVEC		0x305
259 #define CSR_MSCRATCH		0x340
260 #define CSR_MEPC		0x341
261 #define CSR_MCAUSE		0x342
262 #define CSR_MTVAL		0x343
263 #define CSR_MIP			0x344
264 #define CSR_PMPCFG0		0x3a0
265 #define CSR_PMPADDR0		0x3b0
266 #define CSR_MVENDORID		0xf11
267 #define CSR_MARCHID		0xf12
268 #define CSR_MIMPID		0xf13
269 #define CSR_MHARTID		0xf14
270 
271 #ifdef CONFIG_RISCV_M_MODE
272 # define CSR_STATUS	CSR_MSTATUS
273 # define CSR_IE		CSR_MIE
274 # define CSR_TVEC	CSR_MTVEC
275 # define CSR_SCRATCH	CSR_MSCRATCH
276 # define CSR_EPC	CSR_MEPC
277 # define CSR_CAUSE	CSR_MCAUSE
278 # define CSR_TVAL	CSR_MTVAL
279 # define CSR_IP		CSR_MIP
280 
281 # define SR_IE		SR_MIE
282 # define SR_PIE		SR_MPIE
283 # define SR_PP		SR_MPP
284 
285 # define RV_IRQ_SOFT		IRQ_M_SOFT
286 # define RV_IRQ_TIMER	IRQ_M_TIMER
287 # define RV_IRQ_EXT		IRQ_M_EXT
288 #else /* CONFIG_RISCV_M_MODE */
289 # define CSR_STATUS	CSR_SSTATUS
290 # define CSR_IE		CSR_SIE
291 # define CSR_TVEC	CSR_STVEC
292 # define CSR_SCRATCH	CSR_SSCRATCH
293 # define CSR_EPC	CSR_SEPC
294 # define CSR_CAUSE	CSR_SCAUSE
295 # define CSR_TVAL	CSR_STVAL
296 # define CSR_IP		CSR_SIP
297 
298 # define SR_IE		SR_SIE
299 # define SR_PIE		SR_SPIE
300 # define SR_PP		SR_SPP
301 
302 # define RV_IRQ_SOFT		IRQ_S_SOFT
303 # define RV_IRQ_TIMER	IRQ_S_TIMER
304 # define RV_IRQ_EXT		IRQ_S_EXT
305 # define RV_IRQ_PMU	IRQ_PMU_OVF
306 # define SIP_LCOFIP     (_AC(0x1, UL) << IRQ_PMU_OVF)
307 
308 #endif /* !CONFIG_RISCV_M_MODE */
309 
310 /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
311 #define IE_SIE		(_AC(0x1, UL) << RV_IRQ_SOFT)
312 #define IE_TIE		(_AC(0x1, UL) << RV_IRQ_TIMER)
313 #define IE_EIE		(_AC(0x1, UL) << RV_IRQ_EXT)
314 
315 #ifndef __ASSEMBLY__
316 
317 #define csr_swap(csr, val)					\
318 ({								\
319 	unsigned long __v = (unsigned long)(val);		\
320 	__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
321 			      : "=r" (__v) : "rK" (__v)		\
322 			      : "memory");			\
323 	__v;							\
324 })
325 
326 #define csr_read(csr)						\
327 ({								\
328 	register unsigned long __v;				\
329 	__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr)	\
330 			      : "=r" (__v) :			\
331 			      : "memory");			\
332 	__v;							\
333 })
334 
335 #define csr_write(csr, val)					\
336 ({								\
337 	unsigned long __v = (unsigned long)(val);		\
338 	__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0"	\
339 			      : : "rK" (__v)			\
340 			      : "memory");			\
341 })
342 
343 #define csr_read_set(csr, val)					\
344 ({								\
345 	unsigned long __v = (unsigned long)(val);		\
346 	__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
347 			      : "=r" (__v) : "rK" (__v)		\
348 			      : "memory");			\
349 	__v;							\
350 })
351 
352 #define csr_set(csr, val)					\
353 ({								\
354 	unsigned long __v = (unsigned long)(val);		\
355 	__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0"	\
356 			      : : "rK" (__v)			\
357 			      : "memory");			\
358 })
359 
360 #define csr_read_clear(csr, val)				\
361 ({								\
362 	unsigned long __v = (unsigned long)(val);		\
363 	__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
364 			      : "=r" (__v) : "rK" (__v)		\
365 			      : "memory");			\
366 	__v;							\
367 })
368 
369 #define csr_clear(csr, val)					\
370 ({								\
371 	unsigned long __v = (unsigned long)(val);		\
372 	__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0"	\
373 			      : : "rK" (__v)			\
374 			      : "memory");			\
375 })
376 
377 #endif /* __ASSEMBLY__ */
378 
379 #endif /* _ASM_RISCV_CSR_H */
380