1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2015 Regents of the University of California
4  */
5 
6 #ifndef _ASM_RISCV_CACHEFLUSH_H
7 #define _ASM_RISCV_CACHEFLUSH_H
8 
9 #include <asm-generic/cacheflush.h>
10 
11 #undef flush_icache_range
12 #undef flush_icache_user_range
13 #undef flush_dcache_page
14 
15 static inline void local_flush_icache_all(void)
16 {
17 	asm volatile ("fence.i" ::: "memory");
18 }
19 
20 #define PG_dcache_clean PG_arch_1
21 
22 static inline void flush_dcache_page(struct page *page)
23 {
24 	if (test_bit(PG_dcache_clean, &page->flags))
25 		clear_bit(PG_dcache_clean, &page->flags);
26 }
27 
28 /*
29  * RISC-V doesn't have an instruction to flush parts of the instruction cache,
30  * so instead we just flush the whole thing.
31  */
32 #define flush_icache_range(start, end) flush_icache_all()
33 #define flush_icache_user_range(vma, pg, addr, len) flush_icache_all()
34 
35 #ifndef CONFIG_SMP
36 
37 #define flush_icache_all() local_flush_icache_all()
38 #define flush_icache_mm(mm, local) flush_icache_all()
39 
40 #else /* CONFIG_SMP */
41 
42 void flush_icache_all(void);
43 void flush_icache_mm(struct mm_struct *mm, bool local);
44 
45 #endif /* CONFIG_SMP */
46 
47 /*
48  * Bits in sys_riscv_flush_icache()'s flags argument.
49  */
50 #define SYS_RISCV_FLUSH_ICACHE_LOCAL 1UL
51 #define SYS_RISCV_FLUSH_ICACHE_ALL   (SYS_RISCV_FLUSH_ICACHE_LOCAL)
52 
53 #endif /* _ASM_RISCV_CACHEFLUSH_H */
54