1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2015 Regents of the University of California
4  */
5 
6 #ifndef _ASM_RISCV_CACHEFLUSH_H
7 #define _ASM_RISCV_CACHEFLUSH_H
8 
9 #include <linux/mm.h>
10 
11 static inline void local_flush_icache_all(void)
12 {
13 	asm volatile ("fence.i" ::: "memory");
14 }
15 
16 #define PG_dcache_clean PG_arch_1
17 
18 static inline void flush_dcache_page(struct page *page)
19 {
20 	/*
21 	 * HugeTLB pages are always fully mapped and only head page will be
22 	 * set PG_dcache_clean (see comments in flush_icache_pte()).
23 	 */
24 	if (PageHuge(page))
25 		page = compound_head(page);
26 
27 	if (test_bit(PG_dcache_clean, &page->flags))
28 		clear_bit(PG_dcache_clean, &page->flags);
29 }
30 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
31 
32 /*
33  * RISC-V doesn't have an instruction to flush parts of the instruction cache,
34  * so instead we just flush the whole thing.
35  */
36 #define flush_icache_range(start, end) flush_icache_all()
37 #define flush_icache_user_page(vma, pg, addr, len) \
38 	flush_icache_mm(vma->vm_mm, 0)
39 
40 #ifndef CONFIG_SMP
41 
42 #define flush_icache_all() local_flush_icache_all()
43 #define flush_icache_mm(mm, local) flush_icache_all()
44 
45 #else /* CONFIG_SMP */
46 
47 void flush_icache_all(void);
48 void flush_icache_mm(struct mm_struct *mm, bool local);
49 
50 #endif /* CONFIG_SMP */
51 
52 extern unsigned int riscv_cbom_block_size;
53 extern unsigned int riscv_cboz_block_size;
54 void riscv_init_cbo_blocksizes(void);
55 
56 #ifdef CONFIG_RISCV_DMA_NONCOHERENT
57 void riscv_noncoherent_supported(void);
58 #else
59 static inline void riscv_noncoherent_supported(void) {}
60 #endif
61 
62 /*
63  * Bits in sys_riscv_flush_icache()'s flags argument.
64  */
65 #define SYS_RISCV_FLUSH_ICACHE_LOCAL 1UL
66 #define SYS_RISCV_FLUSH_ICACHE_ALL   (SYS_RISCV_FLUSH_ICACHE_LOCAL)
67 
68 #include <asm-generic/cacheflush.h>
69 
70 #endif /* _ASM_RISCV_CACHEFLUSH_H */
71