1 /* 2 * Based on arch/arm/include/asm/barrier.h 3 * 4 * Copyright (C) 2012 ARM Ltd. 5 * Copyright (C) 2013 Regents of the University of California 6 * Copyright (C) 2017 SiFive 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef _ASM_RISCV_BARRIER_H 22 #define _ASM_RISCV_BARRIER_H 23 24 #ifndef __ASSEMBLY__ 25 26 #define nop() __asm__ __volatile__ ("nop") 27 28 #define RISCV_FENCE(p, s) \ 29 __asm__ __volatile__ ("fence " #p "," #s : : : "memory") 30 31 /* These barriers need to enforce ordering on both devices or memory. */ 32 #define mb() RISCV_FENCE(iorw,iorw) 33 #define rmb() RISCV_FENCE(ir,ir) 34 #define wmb() RISCV_FENCE(ow,ow) 35 36 /* These barriers do not need to enforce ordering on devices, just memory. */ 37 #define smp_mb() RISCV_FENCE(rw,rw) 38 #define smp_rmb() RISCV_FENCE(r,r) 39 #define smp_wmb() RISCV_FENCE(w,w) 40 41 #include <asm-generic/barrier.h> 42 43 #endif /* __ASSEMBLY__ */ 44 45 #endif /* _ASM_RISCV_BARRIER_H */ 46