1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 Alibaba Group Holding Limited. 4 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8 9/ { 10 compatible = "thead,th1520"; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 cpus: cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 timebase-frequency = <3000000>; 18 19 c910_0: cpu@0 { 20 compatible = "thead,c910", "riscv"; 21 device_type = "cpu"; 22 riscv,isa = "rv64imafdc"; 23 reg = <0>; 24 i-cache-block-size = <64>; 25 i-cache-size = <65536>; 26 i-cache-sets = <512>; 27 d-cache-block-size = <64>; 28 d-cache-size = <65536>; 29 d-cache-sets = <512>; 30 next-level-cache = <&l2_cache>; 31 mmu-type = "riscv,sv39"; 32 33 cpu0_intc: interrupt-controller { 34 compatible = "riscv,cpu-intc"; 35 interrupt-controller; 36 #interrupt-cells = <1>; 37 }; 38 }; 39 40 c910_1: cpu@1 { 41 compatible = "thead,c910", "riscv"; 42 device_type = "cpu"; 43 riscv,isa = "rv64imafdc"; 44 reg = <1>; 45 i-cache-block-size = <64>; 46 i-cache-size = <65536>; 47 i-cache-sets = <512>; 48 d-cache-block-size = <64>; 49 d-cache-size = <65536>; 50 d-cache-sets = <512>; 51 next-level-cache = <&l2_cache>; 52 mmu-type = "riscv,sv39"; 53 54 cpu1_intc: interrupt-controller { 55 compatible = "riscv,cpu-intc"; 56 interrupt-controller; 57 #interrupt-cells = <1>; 58 }; 59 }; 60 61 c910_2: cpu@2 { 62 compatible = "thead,c910", "riscv"; 63 device_type = "cpu"; 64 riscv,isa = "rv64imafdc"; 65 reg = <2>; 66 i-cache-block-size = <64>; 67 i-cache-size = <65536>; 68 i-cache-sets = <512>; 69 d-cache-block-size = <64>; 70 d-cache-size = <65536>; 71 d-cache-sets = <512>; 72 next-level-cache = <&l2_cache>; 73 mmu-type = "riscv,sv39"; 74 75 cpu2_intc: interrupt-controller { 76 compatible = "riscv,cpu-intc"; 77 interrupt-controller; 78 #interrupt-cells = <1>; 79 }; 80 }; 81 82 c910_3: cpu@3 { 83 compatible = "thead,c910", "riscv"; 84 device_type = "cpu"; 85 riscv,isa = "rv64imafdc"; 86 reg = <3>; 87 i-cache-block-size = <64>; 88 i-cache-size = <65536>; 89 i-cache-sets = <512>; 90 d-cache-block-size = <64>; 91 d-cache-size = <65536>; 92 d-cache-sets = <512>; 93 next-level-cache = <&l2_cache>; 94 mmu-type = "riscv,sv39"; 95 96 cpu3_intc: interrupt-controller { 97 compatible = "riscv,cpu-intc"; 98 interrupt-controller; 99 #interrupt-cells = <1>; 100 }; 101 }; 102 103 l2_cache: l2-cache { 104 compatible = "cache"; 105 cache-block-size = <64>; 106 cache-level = <2>; 107 cache-size = <1048576>; 108 cache-sets = <1024>; 109 cache-unified; 110 }; 111 }; 112 113 osc: oscillator { 114 compatible = "fixed-clock"; 115 clock-output-names = "osc_24m"; 116 #clock-cells = <0>; 117 }; 118 119 osc_32k: 32k-oscillator { 120 compatible = "fixed-clock"; 121 clock-output-names = "osc_32k"; 122 #clock-cells = <0>; 123 }; 124 125 apb_clk: apb-clk-clock { 126 compatible = "fixed-clock"; 127 clock-output-names = "apb_clk"; 128 #clock-cells = <0>; 129 }; 130 131 uart_sclk: uart-sclk-clock { 132 compatible = "fixed-clock"; 133 clock-output-names = "uart_sclk"; 134 #clock-cells = <0>; 135 }; 136 137 soc { 138 compatible = "simple-bus"; 139 interrupt-parent = <&plic>; 140 #address-cells = <2>; 141 #size-cells = <2>; 142 dma-noncoherent; 143 ranges; 144 145 plic: interrupt-controller@ffd8000000 { 146 compatible = "thead,th1520-plic", "thead,c900-plic"; 147 reg = <0xff 0xd8000000 0x0 0x01000000>; 148 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 149 <&cpu1_intc 11>, <&cpu1_intc 9>, 150 <&cpu2_intc 11>, <&cpu2_intc 9>, 151 <&cpu3_intc 11>, <&cpu3_intc 9>; 152 interrupt-controller; 153 #address-cells = <0>; 154 #interrupt-cells = <2>; 155 riscv,ndev = <240>; 156 }; 157 158 clint: timer@ffdc000000 { 159 compatible = "thead,th1520-clint", "thead,c900-clint"; 160 reg = <0xff 0xdc000000 0x0 0x00010000>; 161 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 162 <&cpu1_intc 3>, <&cpu1_intc 7>, 163 <&cpu2_intc 3>, <&cpu2_intc 7>, 164 <&cpu3_intc 3>, <&cpu3_intc 7>; 165 }; 166 167 uart0: serial@ffe7014000 { 168 compatible = "snps,dw-apb-uart"; 169 reg = <0xff 0xe7014000 0x0 0x100>; 170 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; 171 clocks = <&uart_sclk>; 172 reg-shift = <2>; 173 reg-io-width = <4>; 174 status = "disabled"; 175 }; 176 177 uart1: serial@ffe7f00000 { 178 compatible = "snps,dw-apb-uart"; 179 reg = <0xff 0xe7f00000 0x0 0x100>; 180 interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; 181 clocks = <&uart_sclk>; 182 reg-shift = <2>; 183 reg-io-width = <4>; 184 status = "disabled"; 185 }; 186 187 uart3: serial@ffe7f04000 { 188 compatible = "snps,dw-apb-uart"; 189 reg = <0xff 0xe7f04000 0x0 0x100>; 190 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&uart_sclk>; 192 reg-shift = <2>; 193 reg-io-width = <4>; 194 status = "disabled"; 195 }; 196 197 gpio2: gpio@ffe7f34000 { 198 compatible = "snps,dw-apb-gpio"; 199 reg = <0xff 0xe7f34000 0x0 0x1000>; 200 #address-cells = <1>; 201 #size-cells = <0>; 202 203 portc: gpio-controller@0 { 204 compatible = "snps,dw-apb-gpio-port"; 205 gpio-controller; 206 #gpio-cells = <2>; 207 ngpios = <32>; 208 reg = <0>; 209 interrupt-controller; 210 #interrupt-cells = <2>; 211 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; 212 }; 213 }; 214 215 gpio3: gpio@ffe7f38000 { 216 compatible = "snps,dw-apb-gpio"; 217 reg = <0xff 0xe7f38000 0x0 0x1000>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 221 portd: gpio-controller@0 { 222 compatible = "snps,dw-apb-gpio-port"; 223 gpio-controller; 224 #gpio-cells = <2>; 225 ngpios = <32>; 226 reg = <0>; 227 interrupt-controller; 228 #interrupt-cells = <2>; 229 interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; 230 }; 231 }; 232 233 gpio0: gpio@ffec005000 { 234 compatible = "snps,dw-apb-gpio"; 235 reg = <0xff 0xec005000 0x0 0x1000>; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 239 porta: gpio-controller@0 { 240 compatible = "snps,dw-apb-gpio-port"; 241 gpio-controller; 242 #gpio-cells = <2>; 243 ngpios = <32>; 244 reg = <0>; 245 interrupt-controller; 246 #interrupt-cells = <2>; 247 interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; 248 }; 249 }; 250 251 gpio1: gpio@ffec006000 { 252 compatible = "snps,dw-apb-gpio"; 253 reg = <0xff 0xec006000 0x0 0x1000>; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 257 portb: gpio-controller@0 { 258 compatible = "snps,dw-apb-gpio-port"; 259 gpio-controller; 260 #gpio-cells = <2>; 261 ngpios = <32>; 262 reg = <0>; 263 interrupt-controller; 264 #interrupt-cells = <2>; 265 interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; 266 }; 267 }; 268 269 uart2: serial@ffec010000 { 270 compatible = "snps,dw-apb-uart"; 271 reg = <0xff 0xec010000 0x0 0x4000>; 272 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&uart_sclk>; 274 reg-shift = <2>; 275 reg-io-width = <4>; 276 status = "disabled"; 277 }; 278 279 dmac0: dma-controller@ffefc00000 { 280 compatible = "snps,axi-dma-1.01a"; 281 reg = <0xff 0xefc00000 0x0 0x1000>; 282 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&apb_clk>, <&apb_clk>; 284 clock-names = "core-clk", "cfgr-clk"; 285 #dma-cells = <1>; 286 dma-channels = <4>; 287 snps,block-size = <65536 65536 65536 65536>; 288 snps,priority = <0 1 2 3>; 289 snps,dma-masters = <1>; 290 snps,data-width = <4>; 291 snps,axi-max-burst-len = <16>; 292 status = "disabled"; 293 }; 294 295 timer0: timer@ffefc32000 { 296 compatible = "snps,dw-apb-timer"; 297 reg = <0xff 0xefc32000 0x0 0x14>; 298 clocks = <&apb_clk>; 299 clock-names = "timer"; 300 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 301 status = "disabled"; 302 }; 303 304 timer1: timer@ffefc32014 { 305 compatible = "snps,dw-apb-timer"; 306 reg = <0xff 0xefc32014 0x0 0x14>; 307 clocks = <&apb_clk>; 308 clock-names = "timer"; 309 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; 310 status = "disabled"; 311 }; 312 313 timer2: timer@ffefc32028 { 314 compatible = "snps,dw-apb-timer"; 315 reg = <0xff 0xefc32028 0x0 0x14>; 316 clocks = <&apb_clk>; 317 clock-names = "timer"; 318 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 319 status = "disabled"; 320 }; 321 322 timer3: timer@ffefc3203c { 323 compatible = "snps,dw-apb-timer"; 324 reg = <0xff 0xefc3203c 0x0 0x14>; 325 clocks = <&apb_clk>; 326 clock-names = "timer"; 327 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 328 status = "disabled"; 329 }; 330 331 uart4: serial@fff7f08000 { 332 compatible = "snps,dw-apb-uart"; 333 reg = <0xff 0xf7f08000 0x0 0x4000>; 334 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&uart_sclk>; 336 reg-shift = <2>; 337 reg-io-width = <4>; 338 status = "disabled"; 339 }; 340 341 uart5: serial@fff7f0c000 { 342 compatible = "snps,dw-apb-uart"; 343 reg = <0xff 0xf7f0c000 0x0 0x4000>; 344 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&uart_sclk>; 346 reg-shift = <2>; 347 reg-io-width = <4>; 348 status = "disabled"; 349 }; 350 351 timer4: timer@ffffc33000 { 352 compatible = "snps,dw-apb-timer"; 353 reg = <0xff 0xffc33000 0x0 0x14>; 354 clocks = <&apb_clk>; 355 clock-names = "timer"; 356 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 357 status = "disabled"; 358 }; 359 360 timer5: timer@ffffc33014 { 361 compatible = "snps,dw-apb-timer"; 362 reg = <0xff 0xffc33014 0x0 0x14>; 363 clocks = <&apb_clk>; 364 clock-names = "timer"; 365 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; 366 status = "disabled"; 367 }; 368 369 timer6: timer@ffffc33028 { 370 compatible = "snps,dw-apb-timer"; 371 reg = <0xff 0xffc33028 0x0 0x14>; 372 clocks = <&apb_clk>; 373 clock-names = "timer"; 374 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 375 status = "disabled"; 376 }; 377 378 timer7: timer@ffffc3303c { 379 compatible = "snps,dw-apb-timer"; 380 reg = <0xff 0xffc3303c 0x0 0x14>; 381 clocks = <&apb_clk>; 382 clock-names = "timer"; 383 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 384 status = "disabled"; 385 }; 386 387 ao_gpio0: gpio@fffff41000 { 388 compatible = "snps,dw-apb-gpio"; 389 reg = <0xff 0xfff41000 0x0 0x1000>; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 393 porte: gpio-controller@0 { 394 compatible = "snps,dw-apb-gpio-port"; 395 gpio-controller; 396 #gpio-cells = <2>; 397 ngpios = <32>; 398 reg = <0>; 399 interrupt-controller; 400 #interrupt-cells = <2>; 401 interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; 402 }; 403 }; 404 405 ao_gpio1: gpio@fffff52000 { 406 compatible = "snps,dw-apb-gpio"; 407 reg = <0xff 0xfff52000 0x0 0x1000>; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 411 portf: gpio-controller@0 { 412 compatible = "snps,dw-apb-gpio-port"; 413 gpio-controller; 414 #gpio-cells = <2>; 415 ngpios = <32>; 416 reg = <0>; 417 interrupt-controller; 418 #interrupt-cells = <2>; 419 interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; 420 }; 421 }; 422 }; 423}; 424