1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (C) 2022 StarFive Technology Co., Ltd. 4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/starfive,jh7110-crg.h> 9#include <dt-bindings/reset/starfive,jh7110-crg.h> 10 11/ { 12 compatible = "starfive,jh7110"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 S7_0: cpu@0 { 21 compatible = "sifive,s7", "riscv"; 22 reg = <0>; 23 device_type = "cpu"; 24 i-cache-block-size = <64>; 25 i-cache-sets = <64>; 26 i-cache-size = <16384>; 27 next-level-cache = <&ccache>; 28 riscv,isa = "rv64imac_zba_zbb"; 29 status = "disabled"; 30 31 cpu0_intc: interrupt-controller { 32 compatible = "riscv,cpu-intc"; 33 interrupt-controller; 34 #interrupt-cells = <1>; 35 }; 36 }; 37 38 U74_1: cpu@1 { 39 compatible = "sifive,u74-mc", "riscv"; 40 reg = <1>; 41 d-cache-block-size = <64>; 42 d-cache-sets = <64>; 43 d-cache-size = <32768>; 44 d-tlb-sets = <1>; 45 d-tlb-size = <40>; 46 device_type = "cpu"; 47 i-cache-block-size = <64>; 48 i-cache-sets = <64>; 49 i-cache-size = <32768>; 50 i-tlb-sets = <1>; 51 i-tlb-size = <40>; 52 mmu-type = "riscv,sv39"; 53 next-level-cache = <&ccache>; 54 riscv,isa = "rv64imafdc_zba_zbb"; 55 tlb-split; 56 57 cpu1_intc: interrupt-controller { 58 compatible = "riscv,cpu-intc"; 59 interrupt-controller; 60 #interrupt-cells = <1>; 61 }; 62 }; 63 64 U74_2: cpu@2 { 65 compatible = "sifive,u74-mc", "riscv"; 66 reg = <2>; 67 d-cache-block-size = <64>; 68 d-cache-sets = <64>; 69 d-cache-size = <32768>; 70 d-tlb-sets = <1>; 71 d-tlb-size = <40>; 72 device_type = "cpu"; 73 i-cache-block-size = <64>; 74 i-cache-sets = <64>; 75 i-cache-size = <32768>; 76 i-tlb-sets = <1>; 77 i-tlb-size = <40>; 78 mmu-type = "riscv,sv39"; 79 next-level-cache = <&ccache>; 80 riscv,isa = "rv64imafdc_zba_zbb"; 81 tlb-split; 82 83 cpu2_intc: interrupt-controller { 84 compatible = "riscv,cpu-intc"; 85 interrupt-controller; 86 #interrupt-cells = <1>; 87 }; 88 }; 89 90 U74_3: cpu@3 { 91 compatible = "sifive,u74-mc", "riscv"; 92 reg = <3>; 93 d-cache-block-size = <64>; 94 d-cache-sets = <64>; 95 d-cache-size = <32768>; 96 d-tlb-sets = <1>; 97 d-tlb-size = <40>; 98 device_type = "cpu"; 99 i-cache-block-size = <64>; 100 i-cache-sets = <64>; 101 i-cache-size = <32768>; 102 i-tlb-sets = <1>; 103 i-tlb-size = <40>; 104 mmu-type = "riscv,sv39"; 105 next-level-cache = <&ccache>; 106 riscv,isa = "rv64imafdc_zba_zbb"; 107 tlb-split; 108 109 cpu3_intc: interrupt-controller { 110 compatible = "riscv,cpu-intc"; 111 interrupt-controller; 112 #interrupt-cells = <1>; 113 }; 114 }; 115 116 U74_4: cpu@4 { 117 compatible = "sifive,u74-mc", "riscv"; 118 reg = <4>; 119 d-cache-block-size = <64>; 120 d-cache-sets = <64>; 121 d-cache-size = <32768>; 122 d-tlb-sets = <1>; 123 d-tlb-size = <40>; 124 device_type = "cpu"; 125 i-cache-block-size = <64>; 126 i-cache-sets = <64>; 127 i-cache-size = <32768>; 128 i-tlb-sets = <1>; 129 i-tlb-size = <40>; 130 mmu-type = "riscv,sv39"; 131 next-level-cache = <&ccache>; 132 riscv,isa = "rv64imafdc_zba_zbb"; 133 tlb-split; 134 135 cpu4_intc: interrupt-controller { 136 compatible = "riscv,cpu-intc"; 137 interrupt-controller; 138 #interrupt-cells = <1>; 139 }; 140 }; 141 142 cpu-map { 143 cluster0 { 144 core0 { 145 cpu = <&S7_0>; 146 }; 147 148 core1 { 149 cpu = <&U74_1>; 150 }; 151 152 core2 { 153 cpu = <&U74_2>; 154 }; 155 156 core3 { 157 cpu = <&U74_3>; 158 }; 159 160 core4 { 161 cpu = <&U74_4>; 162 }; 163 }; 164 }; 165 }; 166 167 gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { 168 compatible = "fixed-clock"; 169 clock-output-names = "gmac0_rgmii_rxin"; 170 #clock-cells = <0>; 171 }; 172 173 gmac0_rmii_refin: gmac0-rmii-refin-clock { 174 compatible = "fixed-clock"; 175 clock-output-names = "gmac0_rmii_refin"; 176 #clock-cells = <0>; 177 }; 178 179 gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock { 180 compatible = "fixed-clock"; 181 clock-output-names = "gmac1_rgmii_rxin"; 182 #clock-cells = <0>; 183 }; 184 185 gmac1_rmii_refin: gmac1-rmii-refin-clock { 186 compatible = "fixed-clock"; 187 clock-output-names = "gmac1_rmii_refin"; 188 #clock-cells = <0>; 189 }; 190 191 i2srx_bclk_ext: i2srx-bclk-ext-clock { 192 compatible = "fixed-clock"; 193 clock-output-names = "i2srx_bclk_ext"; 194 #clock-cells = <0>; 195 }; 196 197 i2srx_lrck_ext: i2srx-lrck-ext-clock { 198 compatible = "fixed-clock"; 199 clock-output-names = "i2srx_lrck_ext"; 200 #clock-cells = <0>; 201 }; 202 203 i2stx_bclk_ext: i2stx-bclk-ext-clock { 204 compatible = "fixed-clock"; 205 clock-output-names = "i2stx_bclk_ext"; 206 #clock-cells = <0>; 207 }; 208 209 i2stx_lrck_ext: i2stx-lrck-ext-clock { 210 compatible = "fixed-clock"; 211 clock-output-names = "i2stx_lrck_ext"; 212 #clock-cells = <0>; 213 }; 214 215 mclk_ext: mclk-ext-clock { 216 compatible = "fixed-clock"; 217 clock-output-names = "mclk_ext"; 218 #clock-cells = <0>; 219 }; 220 221 osc: oscillator { 222 compatible = "fixed-clock"; 223 clock-output-names = "osc"; 224 #clock-cells = <0>; 225 }; 226 227 rtc_osc: rtc-oscillator { 228 compatible = "fixed-clock"; 229 clock-output-names = "rtc_osc"; 230 #clock-cells = <0>; 231 }; 232 233 tdm_ext: tdm-ext-clock { 234 compatible = "fixed-clock"; 235 clock-output-names = "tdm_ext"; 236 #clock-cells = <0>; 237 }; 238 239 soc { 240 compatible = "simple-bus"; 241 interrupt-parent = <&plic>; 242 #address-cells = <2>; 243 #size-cells = <2>; 244 ranges; 245 246 clint: timer@2000000 { 247 compatible = "starfive,jh7110-clint", "sifive,clint0"; 248 reg = <0x0 0x2000000 0x0 0x10000>; 249 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 250 <&cpu1_intc 3>, <&cpu1_intc 7>, 251 <&cpu2_intc 3>, <&cpu2_intc 7>, 252 <&cpu3_intc 3>, <&cpu3_intc 7>, 253 <&cpu4_intc 3>, <&cpu4_intc 7>; 254 }; 255 256 ccache: cache-controller@2010000 { 257 compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache"; 258 reg = <0x0 0x2010000 0x0 0x4000>; 259 interrupts = <1>, <3>, <4>, <2>; 260 cache-block-size = <64>; 261 cache-level = <2>; 262 cache-sets = <2048>; 263 cache-size = <2097152>; 264 cache-unified; 265 }; 266 267 plic: interrupt-controller@c000000 { 268 compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0"; 269 reg = <0x0 0xc000000 0x0 0x4000000>; 270 interrupts-extended = <&cpu0_intc 11>, 271 <&cpu1_intc 11>, <&cpu1_intc 9>, 272 <&cpu2_intc 11>, <&cpu2_intc 9>, 273 <&cpu3_intc 11>, <&cpu3_intc 9>, 274 <&cpu4_intc 11>, <&cpu4_intc 9>; 275 interrupt-controller; 276 #interrupt-cells = <1>; 277 #address-cells = <0>; 278 riscv,ndev = <136>; 279 }; 280 281 uart0: serial@10000000 { 282 compatible = "snps,dw-apb-uart"; 283 reg = <0x0 0x10000000 0x0 0x10000>; 284 clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>, 285 <&syscrg JH7110_SYSCLK_UART0_APB>; 286 clock-names = "baudclk", "apb_pclk"; 287 resets = <&syscrg JH7110_SYSRST_UART0_APB>; 288 interrupts = <32>; 289 reg-io-width = <4>; 290 reg-shift = <2>; 291 status = "disabled"; 292 }; 293 294 uart1: serial@10010000 { 295 compatible = "snps,dw-apb-uart"; 296 reg = <0x0 0x10010000 0x0 0x10000>; 297 clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>, 298 <&syscrg JH7110_SYSCLK_UART1_APB>; 299 clock-names = "baudclk", "apb_pclk"; 300 resets = <&syscrg JH7110_SYSRST_UART1_APB>; 301 interrupts = <33>; 302 reg-io-width = <4>; 303 reg-shift = <2>; 304 status = "disabled"; 305 }; 306 307 uart2: serial@10020000 { 308 compatible = "snps,dw-apb-uart"; 309 reg = <0x0 0x10020000 0x0 0x10000>; 310 clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>, 311 <&syscrg JH7110_SYSCLK_UART2_APB>; 312 clock-names = "baudclk", "apb_pclk"; 313 resets = <&syscrg JH7110_SYSRST_UART2_APB>; 314 interrupts = <34>; 315 reg-io-width = <4>; 316 reg-shift = <2>; 317 status = "disabled"; 318 }; 319 320 i2c0: i2c@10030000 { 321 compatible = "snps,designware-i2c"; 322 reg = <0x0 0x10030000 0x0 0x10000>; 323 clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>; 324 clock-names = "ref"; 325 resets = <&syscrg JH7110_SYSRST_I2C0_APB>; 326 interrupts = <35>; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 status = "disabled"; 330 }; 331 332 i2c1: i2c@10040000 { 333 compatible = "snps,designware-i2c"; 334 reg = <0x0 0x10040000 0x0 0x10000>; 335 clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>; 336 clock-names = "ref"; 337 resets = <&syscrg JH7110_SYSRST_I2C1_APB>; 338 interrupts = <36>; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 status = "disabled"; 342 }; 343 344 i2c2: i2c@10050000 { 345 compatible = "snps,designware-i2c"; 346 reg = <0x0 0x10050000 0x0 0x10000>; 347 clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>; 348 clock-names = "ref"; 349 resets = <&syscrg JH7110_SYSRST_I2C2_APB>; 350 interrupts = <37>; 351 #address-cells = <1>; 352 #size-cells = <0>; 353 status = "disabled"; 354 }; 355 356 uart3: serial@12000000 { 357 compatible = "snps,dw-apb-uart"; 358 reg = <0x0 0x12000000 0x0 0x10000>; 359 clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>, 360 <&syscrg JH7110_SYSCLK_UART3_APB>; 361 clock-names = "baudclk", "apb_pclk"; 362 resets = <&syscrg JH7110_SYSRST_UART3_APB>; 363 interrupts = <45>; 364 reg-io-width = <4>; 365 reg-shift = <2>; 366 status = "disabled"; 367 }; 368 369 uart4: serial@12010000 { 370 compatible = "snps,dw-apb-uart"; 371 reg = <0x0 0x12010000 0x0 0x10000>; 372 clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>, 373 <&syscrg JH7110_SYSCLK_UART4_APB>; 374 clock-names = "baudclk", "apb_pclk"; 375 resets = <&syscrg JH7110_SYSRST_UART4_APB>; 376 interrupts = <46>; 377 reg-io-width = <4>; 378 reg-shift = <2>; 379 status = "disabled"; 380 }; 381 382 uart5: serial@12020000 { 383 compatible = "snps,dw-apb-uart"; 384 reg = <0x0 0x12020000 0x0 0x10000>; 385 clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>, 386 <&syscrg JH7110_SYSCLK_UART5_APB>; 387 clock-names = "baudclk", "apb_pclk"; 388 resets = <&syscrg JH7110_SYSRST_UART5_APB>; 389 interrupts = <47>; 390 reg-io-width = <4>; 391 reg-shift = <2>; 392 status = "disabled"; 393 }; 394 395 i2c3: i2c@12030000 { 396 compatible = "snps,designware-i2c"; 397 reg = <0x0 0x12030000 0x0 0x10000>; 398 clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>; 399 clock-names = "ref"; 400 resets = <&syscrg JH7110_SYSRST_I2C3_APB>; 401 interrupts = <48>; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 status = "disabled"; 405 }; 406 407 i2c4: i2c@12040000 { 408 compatible = "snps,designware-i2c"; 409 reg = <0x0 0x12040000 0x0 0x10000>; 410 clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>; 411 clock-names = "ref"; 412 resets = <&syscrg JH7110_SYSRST_I2C4_APB>; 413 interrupts = <49>; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 status = "disabled"; 417 }; 418 419 i2c5: i2c@12050000 { 420 compatible = "snps,designware-i2c"; 421 reg = <0x0 0x12050000 0x0 0x10000>; 422 clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>; 423 clock-names = "ref"; 424 resets = <&syscrg JH7110_SYSRST_I2C5_APB>; 425 interrupts = <50>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 status = "disabled"; 429 }; 430 431 i2c6: i2c@12060000 { 432 compatible = "snps,designware-i2c"; 433 reg = <0x0 0x12060000 0x0 0x10000>; 434 clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>; 435 clock-names = "ref"; 436 resets = <&syscrg JH7110_SYSRST_I2C6_APB>; 437 interrupts = <51>; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 status = "disabled"; 441 }; 442 443 syscrg: clock-controller@13020000 { 444 compatible = "starfive,jh7110-syscrg"; 445 reg = <0x0 0x13020000 0x0 0x10000>; 446 clocks = <&osc>, <&gmac1_rmii_refin>, 447 <&gmac1_rgmii_rxin>, 448 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, 449 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, 450 <&tdm_ext>, <&mclk_ext>; 451 clock-names = "osc", "gmac1_rmii_refin", 452 "gmac1_rgmii_rxin", 453 "i2stx_bclk_ext", "i2stx_lrck_ext", 454 "i2srx_bclk_ext", "i2srx_lrck_ext", 455 "tdm_ext", "mclk_ext"; 456 #clock-cells = <1>; 457 #reset-cells = <1>; 458 }; 459 460 sysgpio: pinctrl@13040000 { 461 compatible = "starfive,jh7110-sys-pinctrl"; 462 reg = <0x0 0x13040000 0x0 0x10000>; 463 clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>; 464 resets = <&syscrg JH7110_SYSRST_IOMUX_APB>; 465 interrupts = <86>; 466 interrupt-controller; 467 #interrupt-cells = <2>; 468 gpio-controller; 469 #gpio-cells = <2>; 470 }; 471 472 aoncrg: clock-controller@17000000 { 473 compatible = "starfive,jh7110-aoncrg"; 474 reg = <0x0 0x17000000 0x0 0x10000>; 475 clocks = <&osc>, <&gmac0_rmii_refin>, 476 <&gmac0_rgmii_rxin>, 477 <&syscrg JH7110_SYSCLK_STG_AXIAHB>, 478 <&syscrg JH7110_SYSCLK_APB_BUS>, 479 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>, 480 <&rtc_osc>; 481 clock-names = "osc", "gmac0_rmii_refin", 482 "gmac0_rgmii_rxin", "stg_axiahb", 483 "apb_bus", "gmac0_gtxclk", 484 "rtc_osc"; 485 #clock-cells = <1>; 486 #reset-cells = <1>; 487 }; 488 489 aongpio: pinctrl@17020000 { 490 compatible = "starfive,jh7110-aon-pinctrl"; 491 reg = <0x0 0x17020000 0x0 0x10000>; 492 resets = <&aoncrg JH7110_AONRST_IOMUX>; 493 interrupts = <85>; 494 interrupt-controller; 495 #interrupt-cells = <2>; 496 gpio-controller; 497 #gpio-cells = <2>; 498 }; 499 }; 500}; 501