1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (C) 2022 StarFive Technology Co., Ltd. 4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/starfive,jh7110-crg.h> 9#include <dt-bindings/power/starfive,jh7110-pmu.h> 10#include <dt-bindings/reset/starfive,jh7110-crg.h> 11#include <dt-bindings/thermal/thermal.h> 12 13/ { 14 compatible = "starfive,jh7110"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 S7_0: cpu@0 { 23 compatible = "sifive,s7", "riscv"; 24 reg = <0>; 25 device_type = "cpu"; 26 i-cache-block-size = <64>; 27 i-cache-sets = <64>; 28 i-cache-size = <16384>; 29 next-level-cache = <&ccache>; 30 riscv,isa = "rv64imac_zba_zbb"; 31 status = "disabled"; 32 33 cpu0_intc: interrupt-controller { 34 compatible = "riscv,cpu-intc"; 35 interrupt-controller; 36 #interrupt-cells = <1>; 37 }; 38 }; 39 40 U74_1: cpu@1 { 41 compatible = "sifive,u74-mc", "riscv"; 42 reg = <1>; 43 d-cache-block-size = <64>; 44 d-cache-sets = <64>; 45 d-cache-size = <32768>; 46 d-tlb-sets = <1>; 47 d-tlb-size = <40>; 48 device_type = "cpu"; 49 i-cache-block-size = <64>; 50 i-cache-sets = <64>; 51 i-cache-size = <32768>; 52 i-tlb-sets = <1>; 53 i-tlb-size = <40>; 54 mmu-type = "riscv,sv39"; 55 next-level-cache = <&ccache>; 56 riscv,isa = "rv64imafdc_zba_zbb"; 57 tlb-split; 58 operating-points-v2 = <&cpu_opp>; 59 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; 60 clock-names = "cpu"; 61 #cooling-cells = <2>; 62 63 cpu1_intc: interrupt-controller { 64 compatible = "riscv,cpu-intc"; 65 interrupt-controller; 66 #interrupt-cells = <1>; 67 }; 68 }; 69 70 U74_2: cpu@2 { 71 compatible = "sifive,u74-mc", "riscv"; 72 reg = <2>; 73 d-cache-block-size = <64>; 74 d-cache-sets = <64>; 75 d-cache-size = <32768>; 76 d-tlb-sets = <1>; 77 d-tlb-size = <40>; 78 device_type = "cpu"; 79 i-cache-block-size = <64>; 80 i-cache-sets = <64>; 81 i-cache-size = <32768>; 82 i-tlb-sets = <1>; 83 i-tlb-size = <40>; 84 mmu-type = "riscv,sv39"; 85 next-level-cache = <&ccache>; 86 riscv,isa = "rv64imafdc_zba_zbb"; 87 tlb-split; 88 operating-points-v2 = <&cpu_opp>; 89 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; 90 clock-names = "cpu"; 91 #cooling-cells = <2>; 92 93 cpu2_intc: interrupt-controller { 94 compatible = "riscv,cpu-intc"; 95 interrupt-controller; 96 #interrupt-cells = <1>; 97 }; 98 }; 99 100 U74_3: cpu@3 { 101 compatible = "sifive,u74-mc", "riscv"; 102 reg = <3>; 103 d-cache-block-size = <64>; 104 d-cache-sets = <64>; 105 d-cache-size = <32768>; 106 d-tlb-sets = <1>; 107 d-tlb-size = <40>; 108 device_type = "cpu"; 109 i-cache-block-size = <64>; 110 i-cache-sets = <64>; 111 i-cache-size = <32768>; 112 i-tlb-sets = <1>; 113 i-tlb-size = <40>; 114 mmu-type = "riscv,sv39"; 115 next-level-cache = <&ccache>; 116 riscv,isa = "rv64imafdc_zba_zbb"; 117 tlb-split; 118 operating-points-v2 = <&cpu_opp>; 119 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; 120 clock-names = "cpu"; 121 #cooling-cells = <2>; 122 123 cpu3_intc: interrupt-controller { 124 compatible = "riscv,cpu-intc"; 125 interrupt-controller; 126 #interrupt-cells = <1>; 127 }; 128 }; 129 130 U74_4: cpu@4 { 131 compatible = "sifive,u74-mc", "riscv"; 132 reg = <4>; 133 d-cache-block-size = <64>; 134 d-cache-sets = <64>; 135 d-cache-size = <32768>; 136 d-tlb-sets = <1>; 137 d-tlb-size = <40>; 138 device_type = "cpu"; 139 i-cache-block-size = <64>; 140 i-cache-sets = <64>; 141 i-cache-size = <32768>; 142 i-tlb-sets = <1>; 143 i-tlb-size = <40>; 144 mmu-type = "riscv,sv39"; 145 next-level-cache = <&ccache>; 146 riscv,isa = "rv64imafdc_zba_zbb"; 147 tlb-split; 148 operating-points-v2 = <&cpu_opp>; 149 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; 150 clock-names = "cpu"; 151 #cooling-cells = <2>; 152 153 cpu4_intc: interrupt-controller { 154 compatible = "riscv,cpu-intc"; 155 interrupt-controller; 156 #interrupt-cells = <1>; 157 }; 158 }; 159 160 cpu-map { 161 cluster0 { 162 core0 { 163 cpu = <&S7_0>; 164 }; 165 166 core1 { 167 cpu = <&U74_1>; 168 }; 169 170 core2 { 171 cpu = <&U74_2>; 172 }; 173 174 core3 { 175 cpu = <&U74_3>; 176 }; 177 178 core4 { 179 cpu = <&U74_4>; 180 }; 181 }; 182 }; 183 }; 184 185 cpu_opp: opp-table-0 { 186 compatible = "operating-points-v2"; 187 opp-shared; 188 opp-375000000 { 189 opp-hz = /bits/ 64 <375000000>; 190 opp-microvolt = <800000>; 191 }; 192 opp-500000000 { 193 opp-hz = /bits/ 64 <500000000>; 194 opp-microvolt = <800000>; 195 }; 196 opp-750000000 { 197 opp-hz = /bits/ 64 <750000000>; 198 opp-microvolt = <800000>; 199 }; 200 opp-1500000000 { 201 opp-hz = /bits/ 64 <1500000000>; 202 opp-microvolt = <1040000>; 203 }; 204 }; 205 206 thermal-zones { 207 cpu-thermal { 208 polling-delay-passive = <250>; 209 polling-delay = <15000>; 210 211 thermal-sensors = <&sfctemp>; 212 213 cooling-maps { 214 map0 { 215 trip = <&cpu_alert0>; 216 cooling-device = 217 <&U74_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 218 <&U74_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 219 <&U74_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 220 <&U74_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 221 }; 222 }; 223 224 trips { 225 cpu_alert0: cpu_alert0 { 226 /* milliCelsius */ 227 temperature = <85000>; 228 hysteresis = <2000>; 229 type = "passive"; 230 }; 231 232 cpu_crit { 233 /* milliCelsius */ 234 temperature = <100000>; 235 hysteresis = <2000>; 236 type = "critical"; 237 }; 238 }; 239 }; 240 }; 241 242 dvp_clk: dvp-clock { 243 compatible = "fixed-clock"; 244 clock-output-names = "dvp_clk"; 245 #clock-cells = <0>; 246 }; 247 gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { 248 compatible = "fixed-clock"; 249 clock-output-names = "gmac0_rgmii_rxin"; 250 #clock-cells = <0>; 251 }; 252 253 gmac0_rmii_refin: gmac0-rmii-refin-clock { 254 compatible = "fixed-clock"; 255 clock-output-names = "gmac0_rmii_refin"; 256 #clock-cells = <0>; 257 }; 258 259 gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock { 260 compatible = "fixed-clock"; 261 clock-output-names = "gmac1_rgmii_rxin"; 262 #clock-cells = <0>; 263 }; 264 265 gmac1_rmii_refin: gmac1-rmii-refin-clock { 266 compatible = "fixed-clock"; 267 clock-output-names = "gmac1_rmii_refin"; 268 #clock-cells = <0>; 269 }; 270 271 hdmitx0_pixelclk: hdmitx0-pixel-clock { 272 compatible = "fixed-clock"; 273 clock-output-names = "hdmitx0_pixelclk"; 274 #clock-cells = <0>; 275 }; 276 277 i2srx_bclk_ext: i2srx-bclk-ext-clock { 278 compatible = "fixed-clock"; 279 clock-output-names = "i2srx_bclk_ext"; 280 #clock-cells = <0>; 281 }; 282 283 i2srx_lrck_ext: i2srx-lrck-ext-clock { 284 compatible = "fixed-clock"; 285 clock-output-names = "i2srx_lrck_ext"; 286 #clock-cells = <0>; 287 }; 288 289 i2stx_bclk_ext: i2stx-bclk-ext-clock { 290 compatible = "fixed-clock"; 291 clock-output-names = "i2stx_bclk_ext"; 292 #clock-cells = <0>; 293 }; 294 295 i2stx_lrck_ext: i2stx-lrck-ext-clock { 296 compatible = "fixed-clock"; 297 clock-output-names = "i2stx_lrck_ext"; 298 #clock-cells = <0>; 299 }; 300 301 mclk_ext: mclk-ext-clock { 302 compatible = "fixed-clock"; 303 clock-output-names = "mclk_ext"; 304 #clock-cells = <0>; 305 }; 306 307 osc: oscillator { 308 compatible = "fixed-clock"; 309 clock-output-names = "osc"; 310 #clock-cells = <0>; 311 }; 312 313 rtc_osc: rtc-oscillator { 314 compatible = "fixed-clock"; 315 clock-output-names = "rtc_osc"; 316 #clock-cells = <0>; 317 }; 318 319 stmmac_axi_setup: stmmac-axi-config { 320 snps,lpi_en; 321 snps,wr_osr_lmt = <4>; 322 snps,rd_osr_lmt = <4>; 323 snps,blen = <256 128 64 32 0 0 0>; 324 }; 325 326 tdm_ext: tdm-ext-clock { 327 compatible = "fixed-clock"; 328 clock-output-names = "tdm_ext"; 329 #clock-cells = <0>; 330 }; 331 332 soc { 333 compatible = "simple-bus"; 334 interrupt-parent = <&plic>; 335 #address-cells = <2>; 336 #size-cells = <2>; 337 ranges; 338 339 clint: timer@2000000 { 340 compatible = "starfive,jh7110-clint", "sifive,clint0"; 341 reg = <0x0 0x2000000 0x0 0x10000>; 342 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 343 <&cpu1_intc 3>, <&cpu1_intc 7>, 344 <&cpu2_intc 3>, <&cpu2_intc 7>, 345 <&cpu3_intc 3>, <&cpu3_intc 7>, 346 <&cpu4_intc 3>, <&cpu4_intc 7>; 347 }; 348 349 ccache: cache-controller@2010000 { 350 compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache"; 351 reg = <0x0 0x2010000 0x0 0x4000>; 352 interrupts = <1>, <3>, <4>, <2>; 353 cache-block-size = <64>; 354 cache-level = <2>; 355 cache-sets = <2048>; 356 cache-size = <2097152>; 357 cache-unified; 358 }; 359 360 plic: interrupt-controller@c000000 { 361 compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0"; 362 reg = <0x0 0xc000000 0x0 0x4000000>; 363 interrupts-extended = <&cpu0_intc 11>, 364 <&cpu1_intc 11>, <&cpu1_intc 9>, 365 <&cpu2_intc 11>, <&cpu2_intc 9>, 366 <&cpu3_intc 11>, <&cpu3_intc 9>, 367 <&cpu4_intc 11>, <&cpu4_intc 9>; 368 interrupt-controller; 369 #interrupt-cells = <1>; 370 #address-cells = <0>; 371 riscv,ndev = <136>; 372 }; 373 374 uart0: serial@10000000 { 375 compatible = "snps,dw-apb-uart"; 376 reg = <0x0 0x10000000 0x0 0x10000>; 377 clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>, 378 <&syscrg JH7110_SYSCLK_UART0_APB>; 379 clock-names = "baudclk", "apb_pclk"; 380 resets = <&syscrg JH7110_SYSRST_UART0_APB>; 381 interrupts = <32>; 382 reg-io-width = <4>; 383 reg-shift = <2>; 384 status = "disabled"; 385 }; 386 387 uart1: serial@10010000 { 388 compatible = "snps,dw-apb-uart"; 389 reg = <0x0 0x10010000 0x0 0x10000>; 390 clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>, 391 <&syscrg JH7110_SYSCLK_UART1_APB>; 392 clock-names = "baudclk", "apb_pclk"; 393 resets = <&syscrg JH7110_SYSRST_UART1_APB>; 394 interrupts = <33>; 395 reg-io-width = <4>; 396 reg-shift = <2>; 397 status = "disabled"; 398 }; 399 400 uart2: serial@10020000 { 401 compatible = "snps,dw-apb-uart"; 402 reg = <0x0 0x10020000 0x0 0x10000>; 403 clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>, 404 <&syscrg JH7110_SYSCLK_UART2_APB>; 405 clock-names = "baudclk", "apb_pclk"; 406 resets = <&syscrg JH7110_SYSRST_UART2_APB>; 407 interrupts = <34>; 408 reg-io-width = <4>; 409 reg-shift = <2>; 410 status = "disabled"; 411 }; 412 413 i2c0: i2c@10030000 { 414 compatible = "snps,designware-i2c"; 415 reg = <0x0 0x10030000 0x0 0x10000>; 416 clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>; 417 clock-names = "ref"; 418 resets = <&syscrg JH7110_SYSRST_I2C0_APB>; 419 interrupts = <35>; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 status = "disabled"; 423 }; 424 425 i2c1: i2c@10040000 { 426 compatible = "snps,designware-i2c"; 427 reg = <0x0 0x10040000 0x0 0x10000>; 428 clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>; 429 clock-names = "ref"; 430 resets = <&syscrg JH7110_SYSRST_I2C1_APB>; 431 interrupts = <36>; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 status = "disabled"; 435 }; 436 437 i2c2: i2c@10050000 { 438 compatible = "snps,designware-i2c"; 439 reg = <0x0 0x10050000 0x0 0x10000>; 440 clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>; 441 clock-names = "ref"; 442 resets = <&syscrg JH7110_SYSRST_I2C2_APB>; 443 interrupts = <37>; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 status = "disabled"; 447 }; 448 449 usbphy0: phy@10200000 { 450 compatible = "starfive,jh7110-usb-phy"; 451 reg = <0x0 0x10200000 0x0 0x10000>; 452 clocks = <&syscrg JH7110_SYSCLK_USB_125M>, 453 <&stgcrg JH7110_STGCLK_USB0_APP_125>; 454 clock-names = "125m", "app_125m"; 455 #phy-cells = <0>; 456 }; 457 458 pciephy0: phy@10210000 { 459 compatible = "starfive,jh7110-pcie-phy"; 460 reg = <0x0 0x10210000 0x0 0x10000>; 461 #phy-cells = <0>; 462 }; 463 464 pciephy1: phy@10220000 { 465 compatible = "starfive,jh7110-pcie-phy"; 466 reg = <0x0 0x10220000 0x0 0x10000>; 467 #phy-cells = <0>; 468 }; 469 470 stgcrg: clock-controller@10230000 { 471 compatible = "starfive,jh7110-stgcrg"; 472 reg = <0x0 0x10230000 0x0 0x10000>; 473 clocks = <&osc>, 474 <&syscrg JH7110_SYSCLK_HIFI4_CORE>, 475 <&syscrg JH7110_SYSCLK_STG_AXIAHB>, 476 <&syscrg JH7110_SYSCLK_USB_125M>, 477 <&syscrg JH7110_SYSCLK_CPU_BUS>, 478 <&syscrg JH7110_SYSCLK_HIFI4_AXI>, 479 <&syscrg JH7110_SYSCLK_NOCSTG_BUS>, 480 <&syscrg JH7110_SYSCLK_APB_BUS>; 481 clock-names = "osc", "hifi4_core", 482 "stg_axiahb", "usb_125m", 483 "cpu_bus", "hifi4_axi", 484 "nocstg_bus", "apb_bus"; 485 #clock-cells = <1>; 486 #reset-cells = <1>; 487 }; 488 489 stg_syscon: syscon@10240000 { 490 compatible = "starfive,jh7110-stg-syscon", "syscon"; 491 reg = <0x0 0x10240000 0x0 0x1000>; 492 }; 493 494 uart3: serial@12000000 { 495 compatible = "snps,dw-apb-uart"; 496 reg = <0x0 0x12000000 0x0 0x10000>; 497 clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>, 498 <&syscrg JH7110_SYSCLK_UART3_APB>; 499 clock-names = "baudclk", "apb_pclk"; 500 resets = <&syscrg JH7110_SYSRST_UART3_APB>; 501 interrupts = <45>; 502 reg-io-width = <4>; 503 reg-shift = <2>; 504 status = "disabled"; 505 }; 506 507 uart4: serial@12010000 { 508 compatible = "snps,dw-apb-uart"; 509 reg = <0x0 0x12010000 0x0 0x10000>; 510 clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>, 511 <&syscrg JH7110_SYSCLK_UART4_APB>; 512 clock-names = "baudclk", "apb_pclk"; 513 resets = <&syscrg JH7110_SYSRST_UART4_APB>; 514 interrupts = <46>; 515 reg-io-width = <4>; 516 reg-shift = <2>; 517 status = "disabled"; 518 }; 519 520 uart5: serial@12020000 { 521 compatible = "snps,dw-apb-uart"; 522 reg = <0x0 0x12020000 0x0 0x10000>; 523 clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>, 524 <&syscrg JH7110_SYSCLK_UART5_APB>; 525 clock-names = "baudclk", "apb_pclk"; 526 resets = <&syscrg JH7110_SYSRST_UART5_APB>; 527 interrupts = <47>; 528 reg-io-width = <4>; 529 reg-shift = <2>; 530 status = "disabled"; 531 }; 532 533 i2c3: i2c@12030000 { 534 compatible = "snps,designware-i2c"; 535 reg = <0x0 0x12030000 0x0 0x10000>; 536 clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>; 537 clock-names = "ref"; 538 resets = <&syscrg JH7110_SYSRST_I2C3_APB>; 539 interrupts = <48>; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 status = "disabled"; 543 }; 544 545 i2c4: i2c@12040000 { 546 compatible = "snps,designware-i2c"; 547 reg = <0x0 0x12040000 0x0 0x10000>; 548 clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>; 549 clock-names = "ref"; 550 resets = <&syscrg JH7110_SYSRST_I2C4_APB>; 551 interrupts = <49>; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 status = "disabled"; 555 }; 556 557 i2c5: i2c@12050000 { 558 compatible = "snps,designware-i2c"; 559 reg = <0x0 0x12050000 0x0 0x10000>; 560 clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>; 561 clock-names = "ref"; 562 resets = <&syscrg JH7110_SYSRST_I2C5_APB>; 563 interrupts = <50>; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 status = "disabled"; 567 }; 568 569 i2c6: i2c@12060000 { 570 compatible = "snps,designware-i2c"; 571 reg = <0x0 0x12060000 0x0 0x10000>; 572 clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>; 573 clock-names = "ref"; 574 resets = <&syscrg JH7110_SYSRST_I2C6_APB>; 575 interrupts = <51>; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 status = "disabled"; 579 }; 580 581 sfctemp: temperature-sensor@120e0000 { 582 compatible = "starfive,jh7110-temp"; 583 reg = <0x0 0x120e0000 0x0 0x10000>; 584 clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>, 585 <&syscrg JH7110_SYSCLK_TEMP_APB>; 586 clock-names = "sense", "bus"; 587 resets = <&syscrg JH7110_SYSRST_TEMP_CORE>, 588 <&syscrg JH7110_SYSRST_TEMP_APB>; 589 reset-names = "sense", "bus"; 590 #thermal-sensor-cells = <0>; 591 }; 592 593 syscrg: clock-controller@13020000 { 594 compatible = "starfive,jh7110-syscrg"; 595 reg = <0x0 0x13020000 0x0 0x10000>; 596 clocks = <&osc>, <&gmac1_rmii_refin>, 597 <&gmac1_rgmii_rxin>, 598 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, 599 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, 600 <&tdm_ext>, <&mclk_ext>, 601 <&pllclk JH7110_PLLCLK_PLL0_OUT>, 602 <&pllclk JH7110_PLLCLK_PLL1_OUT>, 603 <&pllclk JH7110_PLLCLK_PLL2_OUT>; 604 clock-names = "osc", "gmac1_rmii_refin", 605 "gmac1_rgmii_rxin", 606 "i2stx_bclk_ext", "i2stx_lrck_ext", 607 "i2srx_bclk_ext", "i2srx_lrck_ext", 608 "tdm_ext", "mclk_ext", 609 "pll0_out", "pll1_out", "pll2_out"; 610 #clock-cells = <1>; 611 #reset-cells = <1>; 612 }; 613 614 sys_syscon: syscon@13030000 { 615 compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; 616 reg = <0x0 0x13030000 0x0 0x1000>; 617 618 pllclk: clock-controller { 619 compatible = "starfive,jh7110-pll"; 620 clocks = <&osc>; 621 #clock-cells = <1>; 622 }; 623 }; 624 625 sysgpio: pinctrl@13040000 { 626 compatible = "starfive,jh7110-sys-pinctrl"; 627 reg = <0x0 0x13040000 0x0 0x10000>; 628 clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>; 629 resets = <&syscrg JH7110_SYSRST_IOMUX_APB>; 630 interrupts = <86>; 631 interrupt-controller; 632 #interrupt-cells = <2>; 633 gpio-controller; 634 #gpio-cells = <2>; 635 }; 636 637 watchdog@13070000 { 638 compatible = "starfive,jh7110-wdt"; 639 reg = <0x0 0x13070000 0x0 0x10000>; 640 clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, 641 <&syscrg JH7110_SYSCLK_WDT_CORE>; 642 clock-names = "apb", "core"; 643 resets = <&syscrg JH7110_SYSRST_WDT_APB>, 644 <&syscrg JH7110_SYSRST_WDT_CORE>; 645 }; 646 647 gmac0: ethernet@16030000 { 648 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; 649 reg = <0x0 0x16030000 0x0 0x10000>; 650 clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>, 651 <&aoncrg JH7110_AONCLK_GMAC0_AHB>, 652 <&syscrg JH7110_SYSCLK_GMAC0_PTP>, 653 <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>, 654 <&syscrg JH7110_SYSCLK_GMAC0_GTXC>; 655 clock-names = "stmmaceth", "pclk", "ptp_ref", 656 "tx", "gtx"; 657 resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>, 658 <&aoncrg JH7110_AONRST_GMAC0_AHB>; 659 reset-names = "stmmaceth", "ahb"; 660 interrupts = <7>, <6>, <5>; 661 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; 662 rx-fifo-depth = <2048>; 663 tx-fifo-depth = <2048>; 664 snps,multicast-filter-bins = <64>; 665 snps,perfect-filter-entries = <8>; 666 snps,fixed-burst; 667 snps,no-pbl-x8; 668 snps,force_thresh_dma_mode; 669 snps,axi-config = <&stmmac_axi_setup>; 670 snps,tso; 671 snps,en-tx-lpi-clockgating; 672 snps,txpbl = <16>; 673 snps,rxpbl = <16>; 674 starfive,syscon = <&aon_syscon 0xc 0x12>; 675 status = "disabled"; 676 }; 677 678 gmac1: ethernet@16040000 { 679 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; 680 reg = <0x0 0x16040000 0x0 0x10000>; 681 clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>, 682 <&syscrg JH7110_SYSCLK_GMAC1_AHB>, 683 <&syscrg JH7110_SYSCLK_GMAC1_PTP>, 684 <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>, 685 <&syscrg JH7110_SYSCLK_GMAC1_GTXC>; 686 clock-names = "stmmaceth", "pclk", "ptp_ref", 687 "tx", "gtx"; 688 resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>, 689 <&syscrg JH7110_SYSRST_GMAC1_AHB>; 690 reset-names = "stmmaceth", "ahb"; 691 interrupts = <78>, <77>, <76>; 692 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; 693 rx-fifo-depth = <2048>; 694 tx-fifo-depth = <2048>; 695 snps,multicast-filter-bins = <64>; 696 snps,perfect-filter-entries = <8>; 697 snps,fixed-burst; 698 snps,no-pbl-x8; 699 snps,force_thresh_dma_mode; 700 snps,axi-config = <&stmmac_axi_setup>; 701 snps,tso; 702 snps,en-tx-lpi-clockgating; 703 snps,txpbl = <16>; 704 snps,rxpbl = <16>; 705 starfive,syscon = <&sys_syscon 0x90 0x2>; 706 status = "disabled"; 707 }; 708 709 aoncrg: clock-controller@17000000 { 710 compatible = "starfive,jh7110-aoncrg"; 711 reg = <0x0 0x17000000 0x0 0x10000>; 712 clocks = <&osc>, <&gmac0_rmii_refin>, 713 <&gmac0_rgmii_rxin>, 714 <&syscrg JH7110_SYSCLK_STG_AXIAHB>, 715 <&syscrg JH7110_SYSCLK_APB_BUS>, 716 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>, 717 <&rtc_osc>; 718 clock-names = "osc", "gmac0_rmii_refin", 719 "gmac0_rgmii_rxin", "stg_axiahb", 720 "apb_bus", "gmac0_gtxclk", 721 "rtc_osc"; 722 #clock-cells = <1>; 723 #reset-cells = <1>; 724 }; 725 726 aon_syscon: syscon@17010000 { 727 compatible = "starfive,jh7110-aon-syscon", "syscon"; 728 reg = <0x0 0x17010000 0x0 0x1000>; 729 #power-domain-cells = <1>; 730 }; 731 732 aongpio: pinctrl@17020000 { 733 compatible = "starfive,jh7110-aon-pinctrl"; 734 reg = <0x0 0x17020000 0x0 0x10000>; 735 resets = <&aoncrg JH7110_AONRST_IOMUX>; 736 interrupts = <85>; 737 interrupt-controller; 738 #interrupt-cells = <2>; 739 gpio-controller; 740 #gpio-cells = <2>; 741 }; 742 743 pwrc: power-controller@17030000 { 744 compatible = "starfive,jh7110-pmu"; 745 reg = <0x0 0x17030000 0x0 0x10000>; 746 interrupts = <111>; 747 #power-domain-cells = <1>; 748 }; 749 750 ispcrg: clock-controller@19810000 { 751 compatible = "starfive,jh7110-ispcrg"; 752 reg = <0x0 0x19810000 0x0 0x10000>; 753 clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, 754 <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>, 755 <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>, 756 <&dvp_clk>; 757 clock-names = "isp_top_core", "isp_top_axi", 758 "noc_bus_isp_axi", "dvp_clk"; 759 resets = <&syscrg JH7110_SYSRST_ISP_TOP>, 760 <&syscrg JH7110_SYSRST_ISP_TOP_AXI>, 761 <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>; 762 #clock-cells = <1>; 763 #reset-cells = <1>; 764 power-domains = <&pwrc JH7110_PD_ISP>; 765 }; 766 767 voutcrg: clock-controller@295c0000 { 768 compatible = "starfive,jh7110-voutcrg"; 769 reg = <0x0 0x295c0000 0x0 0x10000>; 770 clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>, 771 <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, 772 <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, 773 <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, 774 <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, 775 <&hdmitx0_pixelclk>; 776 clock-names = "vout_src", "vout_top_ahb", 777 "vout_top_axi", "vout_top_hdmitx0_mclk", 778 "i2stx0_bclk", "hdmitx0_pixelclk"; 779 resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; 780 #clock-cells = <1>; 781 #reset-cells = <1>; 782 power-domains = <&pwrc JH7110_PD_VOUT>; 783 }; 784 }; 785}; 786