1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (C) 2022 StarFive Technology Co., Ltd. 4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/starfive,jh7110-crg.h> 9#include <dt-bindings/power/starfive,jh7110-pmu.h> 10#include <dt-bindings/reset/starfive,jh7110-crg.h> 11 12/ { 13 compatible = "starfive,jh7110"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 S7_0: cpu@0 { 22 compatible = "sifive,s7", "riscv"; 23 reg = <0>; 24 device_type = "cpu"; 25 i-cache-block-size = <64>; 26 i-cache-sets = <64>; 27 i-cache-size = <16384>; 28 next-level-cache = <&ccache>; 29 riscv,isa = "rv64imac_zba_zbb"; 30 status = "disabled"; 31 32 cpu0_intc: interrupt-controller { 33 compatible = "riscv,cpu-intc"; 34 interrupt-controller; 35 #interrupt-cells = <1>; 36 }; 37 }; 38 39 U74_1: cpu@1 { 40 compatible = "sifive,u74-mc", "riscv"; 41 reg = <1>; 42 d-cache-block-size = <64>; 43 d-cache-sets = <64>; 44 d-cache-size = <32768>; 45 d-tlb-sets = <1>; 46 d-tlb-size = <40>; 47 device_type = "cpu"; 48 i-cache-block-size = <64>; 49 i-cache-sets = <64>; 50 i-cache-size = <32768>; 51 i-tlb-sets = <1>; 52 i-tlb-size = <40>; 53 mmu-type = "riscv,sv39"; 54 next-level-cache = <&ccache>; 55 riscv,isa = "rv64imafdc_zba_zbb"; 56 tlb-split; 57 operating-points-v2 = <&cpu_opp>; 58 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; 59 clock-names = "cpu"; 60 61 cpu1_intc: interrupt-controller { 62 compatible = "riscv,cpu-intc"; 63 interrupt-controller; 64 #interrupt-cells = <1>; 65 }; 66 }; 67 68 U74_2: cpu@2 { 69 compatible = "sifive,u74-mc", "riscv"; 70 reg = <2>; 71 d-cache-block-size = <64>; 72 d-cache-sets = <64>; 73 d-cache-size = <32768>; 74 d-tlb-sets = <1>; 75 d-tlb-size = <40>; 76 device_type = "cpu"; 77 i-cache-block-size = <64>; 78 i-cache-sets = <64>; 79 i-cache-size = <32768>; 80 i-tlb-sets = <1>; 81 i-tlb-size = <40>; 82 mmu-type = "riscv,sv39"; 83 next-level-cache = <&ccache>; 84 riscv,isa = "rv64imafdc_zba_zbb"; 85 tlb-split; 86 operating-points-v2 = <&cpu_opp>; 87 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; 88 clock-names = "cpu"; 89 90 cpu2_intc: interrupt-controller { 91 compatible = "riscv,cpu-intc"; 92 interrupt-controller; 93 #interrupt-cells = <1>; 94 }; 95 }; 96 97 U74_3: cpu@3 { 98 compatible = "sifive,u74-mc", "riscv"; 99 reg = <3>; 100 d-cache-block-size = <64>; 101 d-cache-sets = <64>; 102 d-cache-size = <32768>; 103 d-tlb-sets = <1>; 104 d-tlb-size = <40>; 105 device_type = "cpu"; 106 i-cache-block-size = <64>; 107 i-cache-sets = <64>; 108 i-cache-size = <32768>; 109 i-tlb-sets = <1>; 110 i-tlb-size = <40>; 111 mmu-type = "riscv,sv39"; 112 next-level-cache = <&ccache>; 113 riscv,isa = "rv64imafdc_zba_zbb"; 114 tlb-split; 115 operating-points-v2 = <&cpu_opp>; 116 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; 117 clock-names = "cpu"; 118 119 cpu3_intc: interrupt-controller { 120 compatible = "riscv,cpu-intc"; 121 interrupt-controller; 122 #interrupt-cells = <1>; 123 }; 124 }; 125 126 U74_4: cpu@4 { 127 compatible = "sifive,u74-mc", "riscv"; 128 reg = <4>; 129 d-cache-block-size = <64>; 130 d-cache-sets = <64>; 131 d-cache-size = <32768>; 132 d-tlb-sets = <1>; 133 d-tlb-size = <40>; 134 device_type = "cpu"; 135 i-cache-block-size = <64>; 136 i-cache-sets = <64>; 137 i-cache-size = <32768>; 138 i-tlb-sets = <1>; 139 i-tlb-size = <40>; 140 mmu-type = "riscv,sv39"; 141 next-level-cache = <&ccache>; 142 riscv,isa = "rv64imafdc_zba_zbb"; 143 tlb-split; 144 operating-points-v2 = <&cpu_opp>; 145 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; 146 clock-names = "cpu"; 147 148 cpu4_intc: interrupt-controller { 149 compatible = "riscv,cpu-intc"; 150 interrupt-controller; 151 #interrupt-cells = <1>; 152 }; 153 }; 154 155 cpu-map { 156 cluster0 { 157 core0 { 158 cpu = <&S7_0>; 159 }; 160 161 core1 { 162 cpu = <&U74_1>; 163 }; 164 165 core2 { 166 cpu = <&U74_2>; 167 }; 168 169 core3 { 170 cpu = <&U74_3>; 171 }; 172 173 core4 { 174 cpu = <&U74_4>; 175 }; 176 }; 177 }; 178 }; 179 180 cpu_opp: opp-table-0 { 181 compatible = "operating-points-v2"; 182 opp-shared; 183 opp-375000000 { 184 opp-hz = /bits/ 64 <375000000>; 185 opp-microvolt = <800000>; 186 }; 187 opp-500000000 { 188 opp-hz = /bits/ 64 <500000000>; 189 opp-microvolt = <800000>; 190 }; 191 opp-750000000 { 192 opp-hz = /bits/ 64 <750000000>; 193 opp-microvolt = <800000>; 194 }; 195 opp-1500000000 { 196 opp-hz = /bits/ 64 <1500000000>; 197 opp-microvolt = <1040000>; 198 }; 199 }; 200 201 dvp_clk: dvp-clock { 202 compatible = "fixed-clock"; 203 clock-output-names = "dvp_clk"; 204 #clock-cells = <0>; 205 }; 206 207 gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { 208 compatible = "fixed-clock"; 209 clock-output-names = "gmac0_rgmii_rxin"; 210 #clock-cells = <0>; 211 }; 212 213 gmac0_rmii_refin: gmac0-rmii-refin-clock { 214 compatible = "fixed-clock"; 215 clock-output-names = "gmac0_rmii_refin"; 216 #clock-cells = <0>; 217 }; 218 219 gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock { 220 compatible = "fixed-clock"; 221 clock-output-names = "gmac1_rgmii_rxin"; 222 #clock-cells = <0>; 223 }; 224 225 gmac1_rmii_refin: gmac1-rmii-refin-clock { 226 compatible = "fixed-clock"; 227 clock-output-names = "gmac1_rmii_refin"; 228 #clock-cells = <0>; 229 }; 230 231 hdmitx0_pixelclk: hdmitx0-pixel-clock { 232 compatible = "fixed-clock"; 233 clock-output-names = "hdmitx0_pixelclk"; 234 #clock-cells = <0>; 235 }; 236 237 i2srx_bclk_ext: i2srx-bclk-ext-clock { 238 compatible = "fixed-clock"; 239 clock-output-names = "i2srx_bclk_ext"; 240 #clock-cells = <0>; 241 }; 242 243 i2srx_lrck_ext: i2srx-lrck-ext-clock { 244 compatible = "fixed-clock"; 245 clock-output-names = "i2srx_lrck_ext"; 246 #clock-cells = <0>; 247 }; 248 249 i2stx_bclk_ext: i2stx-bclk-ext-clock { 250 compatible = "fixed-clock"; 251 clock-output-names = "i2stx_bclk_ext"; 252 #clock-cells = <0>; 253 }; 254 255 i2stx_lrck_ext: i2stx-lrck-ext-clock { 256 compatible = "fixed-clock"; 257 clock-output-names = "i2stx_lrck_ext"; 258 #clock-cells = <0>; 259 }; 260 261 mclk_ext: mclk-ext-clock { 262 compatible = "fixed-clock"; 263 clock-output-names = "mclk_ext"; 264 #clock-cells = <0>; 265 }; 266 267 osc: oscillator { 268 compatible = "fixed-clock"; 269 clock-output-names = "osc"; 270 #clock-cells = <0>; 271 }; 272 273 rtc_osc: rtc-oscillator { 274 compatible = "fixed-clock"; 275 clock-output-names = "rtc_osc"; 276 #clock-cells = <0>; 277 }; 278 279 tdm_ext: tdm-ext-clock { 280 compatible = "fixed-clock"; 281 clock-output-names = "tdm_ext"; 282 #clock-cells = <0>; 283 }; 284 285 soc { 286 compatible = "simple-bus"; 287 interrupt-parent = <&plic>; 288 #address-cells = <2>; 289 #size-cells = <2>; 290 ranges; 291 292 clint: timer@2000000 { 293 compatible = "starfive,jh7110-clint", "sifive,clint0"; 294 reg = <0x0 0x2000000 0x0 0x10000>; 295 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 296 <&cpu1_intc 3>, <&cpu1_intc 7>, 297 <&cpu2_intc 3>, <&cpu2_intc 7>, 298 <&cpu3_intc 3>, <&cpu3_intc 7>, 299 <&cpu4_intc 3>, <&cpu4_intc 7>; 300 }; 301 302 ccache: cache-controller@2010000 { 303 compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache"; 304 reg = <0x0 0x2010000 0x0 0x4000>; 305 interrupts = <1>, <3>, <4>, <2>; 306 cache-block-size = <64>; 307 cache-level = <2>; 308 cache-sets = <2048>; 309 cache-size = <2097152>; 310 cache-unified; 311 }; 312 313 plic: interrupt-controller@c000000 { 314 compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0"; 315 reg = <0x0 0xc000000 0x0 0x4000000>; 316 interrupts-extended = <&cpu0_intc 11>, 317 <&cpu1_intc 11>, <&cpu1_intc 9>, 318 <&cpu2_intc 11>, <&cpu2_intc 9>, 319 <&cpu3_intc 11>, <&cpu3_intc 9>, 320 <&cpu4_intc 11>, <&cpu4_intc 9>; 321 interrupt-controller; 322 #interrupt-cells = <1>; 323 #address-cells = <0>; 324 riscv,ndev = <136>; 325 }; 326 327 uart0: serial@10000000 { 328 compatible = "snps,dw-apb-uart"; 329 reg = <0x0 0x10000000 0x0 0x10000>; 330 clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>, 331 <&syscrg JH7110_SYSCLK_UART0_APB>; 332 clock-names = "baudclk", "apb_pclk"; 333 resets = <&syscrg JH7110_SYSRST_UART0_APB>; 334 interrupts = <32>; 335 reg-io-width = <4>; 336 reg-shift = <2>; 337 status = "disabled"; 338 }; 339 340 uart1: serial@10010000 { 341 compatible = "snps,dw-apb-uart"; 342 reg = <0x0 0x10010000 0x0 0x10000>; 343 clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>, 344 <&syscrg JH7110_SYSCLK_UART1_APB>; 345 clock-names = "baudclk", "apb_pclk"; 346 resets = <&syscrg JH7110_SYSRST_UART1_APB>; 347 interrupts = <33>; 348 reg-io-width = <4>; 349 reg-shift = <2>; 350 status = "disabled"; 351 }; 352 353 uart2: serial@10020000 { 354 compatible = "snps,dw-apb-uart"; 355 reg = <0x0 0x10020000 0x0 0x10000>; 356 clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>, 357 <&syscrg JH7110_SYSCLK_UART2_APB>; 358 clock-names = "baudclk", "apb_pclk"; 359 resets = <&syscrg JH7110_SYSRST_UART2_APB>; 360 interrupts = <34>; 361 reg-io-width = <4>; 362 reg-shift = <2>; 363 status = "disabled"; 364 }; 365 366 i2c0: i2c@10030000 { 367 compatible = "snps,designware-i2c"; 368 reg = <0x0 0x10030000 0x0 0x10000>; 369 clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>; 370 clock-names = "ref"; 371 resets = <&syscrg JH7110_SYSRST_I2C0_APB>; 372 interrupts = <35>; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 status = "disabled"; 376 }; 377 378 i2c1: i2c@10040000 { 379 compatible = "snps,designware-i2c"; 380 reg = <0x0 0x10040000 0x0 0x10000>; 381 clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>; 382 clock-names = "ref"; 383 resets = <&syscrg JH7110_SYSRST_I2C1_APB>; 384 interrupts = <36>; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 status = "disabled"; 388 }; 389 390 i2c2: i2c@10050000 { 391 compatible = "snps,designware-i2c"; 392 reg = <0x0 0x10050000 0x0 0x10000>; 393 clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>; 394 clock-names = "ref"; 395 resets = <&syscrg JH7110_SYSRST_I2C2_APB>; 396 interrupts = <37>; 397 #address-cells = <1>; 398 #size-cells = <0>; 399 status = "disabled"; 400 }; 401 402 stgcrg: clock-controller@10230000 { 403 compatible = "starfive,jh7110-stgcrg"; 404 reg = <0x0 0x10230000 0x0 0x10000>; 405 clocks = <&osc>, 406 <&syscrg JH7110_SYSCLK_HIFI4_CORE>, 407 <&syscrg JH7110_SYSCLK_STG_AXIAHB>, 408 <&syscrg JH7110_SYSCLK_USB_125M>, 409 <&syscrg JH7110_SYSCLK_CPU_BUS>, 410 <&syscrg JH7110_SYSCLK_HIFI4_AXI>, 411 <&syscrg JH7110_SYSCLK_NOCSTG_BUS>, 412 <&syscrg JH7110_SYSCLK_APB_BUS>; 413 clock-names = "osc", "hifi4_core", 414 "stg_axiahb", "usb_125m", 415 "cpu_bus", "hifi4_axi", 416 "nocstg_bus", "apb_bus"; 417 #clock-cells = <1>; 418 #reset-cells = <1>; 419 }; 420 421 stg_syscon: syscon@10240000 { 422 compatible = "starfive,jh7110-stg-syscon", "syscon"; 423 reg = <0x0 0x10240000 0x0 0x1000>; 424 }; 425 426 uart3: serial@12000000 { 427 compatible = "snps,dw-apb-uart"; 428 reg = <0x0 0x12000000 0x0 0x10000>; 429 clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>, 430 <&syscrg JH7110_SYSCLK_UART3_APB>; 431 clock-names = "baudclk", "apb_pclk"; 432 resets = <&syscrg JH7110_SYSRST_UART3_APB>; 433 interrupts = <45>; 434 reg-io-width = <4>; 435 reg-shift = <2>; 436 status = "disabled"; 437 }; 438 439 uart4: serial@12010000 { 440 compatible = "snps,dw-apb-uart"; 441 reg = <0x0 0x12010000 0x0 0x10000>; 442 clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>, 443 <&syscrg JH7110_SYSCLK_UART4_APB>; 444 clock-names = "baudclk", "apb_pclk"; 445 resets = <&syscrg JH7110_SYSRST_UART4_APB>; 446 interrupts = <46>; 447 reg-io-width = <4>; 448 reg-shift = <2>; 449 status = "disabled"; 450 }; 451 452 uart5: serial@12020000 { 453 compatible = "snps,dw-apb-uart"; 454 reg = <0x0 0x12020000 0x0 0x10000>; 455 clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>, 456 <&syscrg JH7110_SYSCLK_UART5_APB>; 457 clock-names = "baudclk", "apb_pclk"; 458 resets = <&syscrg JH7110_SYSRST_UART5_APB>; 459 interrupts = <47>; 460 reg-io-width = <4>; 461 reg-shift = <2>; 462 status = "disabled"; 463 }; 464 465 i2c3: i2c@12030000 { 466 compatible = "snps,designware-i2c"; 467 reg = <0x0 0x12030000 0x0 0x10000>; 468 clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>; 469 clock-names = "ref"; 470 resets = <&syscrg JH7110_SYSRST_I2C3_APB>; 471 interrupts = <48>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 status = "disabled"; 475 }; 476 477 i2c4: i2c@12040000 { 478 compatible = "snps,designware-i2c"; 479 reg = <0x0 0x12040000 0x0 0x10000>; 480 clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>; 481 clock-names = "ref"; 482 resets = <&syscrg JH7110_SYSRST_I2C4_APB>; 483 interrupts = <49>; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 status = "disabled"; 487 }; 488 489 i2c5: i2c@12050000 { 490 compatible = "snps,designware-i2c"; 491 reg = <0x0 0x12050000 0x0 0x10000>; 492 clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>; 493 clock-names = "ref"; 494 resets = <&syscrg JH7110_SYSRST_I2C5_APB>; 495 interrupts = <50>; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 status = "disabled"; 499 }; 500 501 i2c6: i2c@12060000 { 502 compatible = "snps,designware-i2c"; 503 reg = <0x0 0x12060000 0x0 0x10000>; 504 clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>; 505 clock-names = "ref"; 506 resets = <&syscrg JH7110_SYSRST_I2C6_APB>; 507 interrupts = <51>; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 status = "disabled"; 511 }; 512 513 syscrg: clock-controller@13020000 { 514 compatible = "starfive,jh7110-syscrg"; 515 reg = <0x0 0x13020000 0x0 0x10000>; 516 clocks = <&osc>, <&gmac1_rmii_refin>, 517 <&gmac1_rgmii_rxin>, 518 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, 519 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, 520 <&tdm_ext>, <&mclk_ext>; 521 clock-names = "osc", "gmac1_rmii_refin", 522 "gmac1_rgmii_rxin", 523 "i2stx_bclk_ext", "i2stx_lrck_ext", 524 "i2srx_bclk_ext", "i2srx_lrck_ext", 525 "tdm_ext", "mclk_ext"; 526 #clock-cells = <1>; 527 #reset-cells = <1>; 528 }; 529 530 sys_syscon: syscon@13030000 { 531 compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; 532 reg = <0x0 0x13030000 0x0 0x1000>; 533 534 pllclk: clock-controller { 535 compatible = "starfive,jh7110-pll"; 536 clocks = <&osc>; 537 #clock-cells = <1>; 538 }; 539 }; 540 541 sysgpio: pinctrl@13040000 { 542 compatible = "starfive,jh7110-sys-pinctrl"; 543 reg = <0x0 0x13040000 0x0 0x10000>; 544 clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>; 545 resets = <&syscrg JH7110_SYSRST_IOMUX_APB>; 546 interrupts = <86>; 547 interrupt-controller; 548 #interrupt-cells = <2>; 549 gpio-controller; 550 #gpio-cells = <2>; 551 }; 552 553 watchdog@13070000 { 554 compatible = "starfive,jh7110-wdt"; 555 reg = <0x0 0x13070000 0x0 0x10000>; 556 clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, 557 <&syscrg JH7110_SYSCLK_WDT_CORE>; 558 clock-names = "apb", "core"; 559 resets = <&syscrg JH7110_SYSRST_WDT_APB>, 560 <&syscrg JH7110_SYSRST_WDT_CORE>; 561 }; 562 563 aoncrg: clock-controller@17000000 { 564 compatible = "starfive,jh7110-aoncrg"; 565 reg = <0x0 0x17000000 0x0 0x10000>; 566 clocks = <&osc>, <&gmac0_rmii_refin>, 567 <&gmac0_rgmii_rxin>, 568 <&syscrg JH7110_SYSCLK_STG_AXIAHB>, 569 <&syscrg JH7110_SYSCLK_APB_BUS>, 570 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>, 571 <&rtc_osc>; 572 clock-names = "osc", "gmac0_rmii_refin", 573 "gmac0_rgmii_rxin", "stg_axiahb", 574 "apb_bus", "gmac0_gtxclk", 575 "rtc_osc"; 576 #clock-cells = <1>; 577 #reset-cells = <1>; 578 }; 579 580 aon_syscon: syscon@17010000 { 581 compatible = "starfive,jh7110-aon-syscon", "syscon"; 582 reg = <0x0 0x17010000 0x0 0x1000>; 583 #power-domain-cells = <1>; 584 }; 585 586 aongpio: pinctrl@17020000 { 587 compatible = "starfive,jh7110-aon-pinctrl"; 588 reg = <0x0 0x17020000 0x0 0x10000>; 589 resets = <&aoncrg JH7110_AONRST_IOMUX>; 590 interrupts = <85>; 591 interrupt-controller; 592 #interrupt-cells = <2>; 593 gpio-controller; 594 #gpio-cells = <2>; 595 }; 596 597 pwrc: power-controller@17030000 { 598 compatible = "starfive,jh7110-pmu"; 599 reg = <0x0 0x17030000 0x0 0x10000>; 600 interrupts = <111>; 601 #power-domain-cells = <1>; 602 }; 603 604 ispcrg: clock-controller@19810000 { 605 compatible = "starfive,jh7110-ispcrg"; 606 reg = <0x0 0x19810000 0x0 0x10000>; 607 clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, 608 <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>, 609 <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>, 610 <&dvp_clk>; 611 clock-names = "isp_top_core", "isp_top_axi", 612 "noc_bus_isp_axi", "dvp_clk"; 613 resets = <&syscrg JH7110_SYSRST_ISP_TOP>, 614 <&syscrg JH7110_SYSRST_ISP_TOP_AXI>, 615 <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>; 616 #clock-cells = <1>; 617 #reset-cells = <1>; 618 power-domains = <&pwrc JH7110_PD_ISP>; 619 }; 620 621 voutcrg: clock-controller@295c0000 { 622 compatible = "starfive,jh7110-voutcrg"; 623 reg = <0x0 0x295c0000 0x0 0x10000>; 624 clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>, 625 <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, 626 <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, 627 <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, 628 <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, 629 <&hdmitx0_pixelclk>; 630 clock-names = "vout_src", "vout_top_ahb", 631 "vout_top_axi", "vout_top_hdmitx0_mclk", 632 "i2stx0_bclk", "hdmitx0_pixelclk"; 633 resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; 634 #clock-cells = <1>; 635 #reset-cells = <1>; 636 power-domains = <&pwrc JH7110_PD_VOUT>; 637 }; 638 }; 639}; 640