1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
5 */
6
7/dts-v1/;
8#include "jh7110.dtsi"
9#include "jh7110-pinfunc.h"
10#include <dt-bindings/gpio/gpio.h>
11
12/ {
13	aliases {
14		ethernet0 = &gmac0;
15		ethernet1 = &gmac1;
16		i2c0 = &i2c0;
17		i2c2 = &i2c2;
18		i2c5 = &i2c5;
19		i2c6 = &i2c6;
20		mmc0 = &mmc0;
21		mmc1 = &mmc1;
22		serial0 = &uart0;
23	};
24
25	chosen {
26		stdout-path = "serial0:115200n8";
27	};
28
29	cpus {
30		timebase-frequency = <4000000>;
31	};
32
33	memory@40000000 {
34		device_type = "memory";
35		reg = <0x0 0x40000000 0x1 0x0>;
36	};
37
38	gpio-restart {
39		compatible = "gpio-restart";
40		gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
41		priority = <224>;
42	};
43};
44
45&dvp_clk {
46	clock-frequency = <74250000>;
47};
48
49&gmac0_rgmii_rxin {
50	clock-frequency = <125000000>;
51};
52
53&gmac0_rmii_refin {
54	clock-frequency = <50000000>;
55};
56
57&gmac1_rgmii_rxin {
58	clock-frequency = <125000000>;
59};
60
61&gmac1_rmii_refin {
62	clock-frequency = <50000000>;
63};
64
65&hdmitx0_pixelclk {
66	clock-frequency = <297000000>;
67};
68
69&i2srx_bclk_ext {
70	clock-frequency = <12288000>;
71};
72
73&i2srx_lrck_ext {
74	clock-frequency = <192000>;
75};
76
77&i2stx_bclk_ext {
78	clock-frequency = <12288000>;
79};
80
81&i2stx_lrck_ext {
82	clock-frequency = <192000>;
83};
84
85&mclk_ext {
86	clock-frequency = <12288000>;
87};
88
89&osc {
90	clock-frequency = <24000000>;
91};
92
93&rtc_osc {
94	clock-frequency = <32768>;
95};
96
97&tdm_ext {
98	clock-frequency = <49152000>;
99};
100
101&gmac0 {
102	phy-handle = <&phy0>;
103	phy-mode = "rgmii-id";
104	status = "okay";
105
106	mdio {
107		#address-cells = <1>;
108		#size-cells = <0>;
109		compatible = "snps,dwmac-mdio";
110
111		phy0: ethernet-phy@0 {
112			reg = <0>;
113		};
114	};
115};
116
117&gmac1 {
118	phy-handle = <&phy1>;
119	phy-mode = "rgmii-id";
120	status = "okay";
121
122	mdio {
123		#address-cells = <1>;
124		#size-cells = <0>;
125		compatible = "snps,dwmac-mdio";
126
127		phy1: ethernet-phy@1 {
128			reg = <0>;
129		};
130	};
131};
132
133&i2c0 {
134	clock-frequency = <100000>;
135	i2c-sda-hold-time-ns = <300>;
136	i2c-sda-falling-time-ns = <510>;
137	i2c-scl-falling-time-ns = <510>;
138	pinctrl-names = "default";
139	pinctrl-0 = <&i2c0_pins>;
140	status = "okay";
141};
142
143&i2c2 {
144	clock-frequency = <100000>;
145	i2c-sda-hold-time-ns = <300>;
146	i2c-sda-falling-time-ns = <510>;
147	i2c-scl-falling-time-ns = <510>;
148	pinctrl-names = "default";
149	pinctrl-0 = <&i2c2_pins>;
150	status = "okay";
151};
152
153&i2c5 {
154	clock-frequency = <100000>;
155	i2c-sda-hold-time-ns = <300>;
156	i2c-sda-falling-time-ns = <510>;
157	i2c-scl-falling-time-ns = <510>;
158	pinctrl-names = "default";
159	pinctrl-0 = <&i2c5_pins>;
160	status = "okay";
161
162	axp15060: pmic@36 {
163		compatible = "x-powers,axp15060";
164		reg = <0x36>;
165		interrupt-controller;
166		#interrupt-cells = <1>;
167
168		regulators {
169			vcc_3v3: dcdc1 {
170				regulator-boot-on;
171				regulator-always-on;
172				regulator-min-microvolt = <3300000>;
173				regulator-max-microvolt = <3300000>;
174				regulator-name = "vcc_3v3";
175			};
176
177			vdd_cpu: dcdc2 {
178				regulator-always-on;
179				regulator-min-microvolt = <500000>;
180				regulator-max-microvolt = <1540000>;
181				regulator-name = "vdd-cpu";
182			};
183
184			emmc_vdd: aldo4 {
185				regulator-boot-on;
186				regulator-always-on;
187				regulator-min-microvolt = <1800000>;
188				regulator-max-microvolt = <1800000>;
189				regulator-name = "emmc_vdd";
190			};
191		};
192	};
193};
194
195&i2c6 {
196	clock-frequency = <100000>;
197	i2c-sda-hold-time-ns = <300>;
198	i2c-sda-falling-time-ns = <510>;
199	i2c-scl-falling-time-ns = <510>;
200	pinctrl-names = "default";
201	pinctrl-0 = <&i2c6_pins>;
202	status = "okay";
203};
204
205&mmc0 {
206	max-frequency = <100000000>;
207	bus-width = <8>;
208	cap-mmc-highspeed;
209	mmc-ddr-1_8v;
210	mmc-hs200-1_8v;
211	non-removable;
212	cap-mmc-hw-reset;
213	post-power-on-delay-ms = <200>;
214	pinctrl-names = "default";
215	pinctrl-0 = <&mmc0_pins>;
216	vmmc-supply = <&vcc_3v3>;
217	vqmmc-supply = <&emmc_vdd>;
218	status = "okay";
219};
220
221&mmc1 {
222	max-frequency = <100000000>;
223	bus-width = <4>;
224	no-sdio;
225	no-mmc;
226	broken-cd;
227	cap-sd-highspeed;
228	post-power-on-delay-ms = <200>;
229	pinctrl-names = "default";
230	pinctrl-0 = <&mmc1_pins>;
231	status = "okay";
232};
233
234&qspi {
235	#address-cells = <1>;
236	#size-cells = <0>;
237	status = "okay";
238
239	nor_flash: flash@0 {
240		compatible = "jedec,spi-nor";
241		reg = <0>;
242		cdns,read-delay = <5>;
243		spi-max-frequency = <12000000>;
244		cdns,tshsl-ns = <1>;
245		cdns,tsd2d-ns = <1>;
246		cdns,tchsh-ns = <1>;
247		cdns,tslch-ns = <1>;
248
249		partitions {
250			compatible = "fixed-partitions";
251			#address-cells = <1>;
252			#size-cells = <1>;
253
254			spl@0 {
255				reg = <0x0 0x80000>;
256			};
257			uboot-env@f0000 {
258				reg = <0xf0000 0x10000>;
259			};
260			uboot@100000 {
261				reg = <0x100000 0x400000>;
262			};
263			reserved-data@600000 {
264				reg = <0x600000 0xa00000>;
265			};
266		};
267	};
268};
269
270&spi0 {
271	pinctrl-names = "default";
272	pinctrl-0 = <&spi0_pins>;
273	status = "okay";
274
275	spi_dev0: spi@0 {
276		compatible = "rohm,dh2228fv";
277		reg = <0>;
278		spi-max-frequency = <10000000>;
279	};
280};
281
282&sysgpio {
283	i2c0_pins: i2c0-0 {
284		i2c-pins {
285			pinmux = <GPIOMUX(57, GPOUT_LOW,
286					      GPOEN_SYS_I2C0_CLK,
287					      GPI_SYS_I2C0_CLK)>,
288				 <GPIOMUX(58, GPOUT_LOW,
289					      GPOEN_SYS_I2C0_DATA,
290					      GPI_SYS_I2C0_DATA)>;
291			bias-disable; /* external pull-up */
292			input-enable;
293			input-schmitt-enable;
294		};
295	};
296
297	i2c2_pins: i2c2-0 {
298		i2c-pins {
299			pinmux = <GPIOMUX(3, GPOUT_LOW,
300					     GPOEN_SYS_I2C2_CLK,
301					     GPI_SYS_I2C2_CLK)>,
302				 <GPIOMUX(2, GPOUT_LOW,
303					     GPOEN_SYS_I2C2_DATA,
304					     GPI_SYS_I2C2_DATA)>;
305			bias-disable; /* external pull-up */
306			input-enable;
307			input-schmitt-enable;
308		};
309	};
310
311	i2c5_pins: i2c5-0 {
312		i2c-pins {
313			pinmux = <GPIOMUX(19, GPOUT_LOW,
314					      GPOEN_SYS_I2C5_CLK,
315					      GPI_SYS_I2C5_CLK)>,
316				 <GPIOMUX(20, GPOUT_LOW,
317					      GPOEN_SYS_I2C5_DATA,
318					      GPI_SYS_I2C5_DATA)>;
319			bias-disable; /* external pull-up */
320			input-enable;
321			input-schmitt-enable;
322		};
323	};
324
325	i2c6_pins: i2c6-0 {
326		i2c-pins {
327			pinmux = <GPIOMUX(16, GPOUT_LOW,
328					      GPOEN_SYS_I2C6_CLK,
329					      GPI_SYS_I2C6_CLK)>,
330				 <GPIOMUX(17, GPOUT_LOW,
331					      GPOEN_SYS_I2C6_DATA,
332					      GPI_SYS_I2C6_DATA)>;
333			bias-disable; /* external pull-up */
334			input-enable;
335			input-schmitt-enable;
336		};
337	};
338
339	mmc0_pins: mmc0-0 {
340		 rst-pins {
341			pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
342					      GPOEN_ENABLE,
343					      GPI_NONE)>;
344			bias-pull-up;
345			drive-strength = <12>;
346			input-disable;
347			input-schmitt-disable;
348			slew-rate = <0>;
349		};
350
351		mmc-pins {
352			pinmux = <PINMUX(64, 0)>,
353				 <PINMUX(65, 0)>,
354				 <PINMUX(66, 0)>,
355				 <PINMUX(67, 0)>,
356				 <PINMUX(68, 0)>,
357				 <PINMUX(69, 0)>,
358				 <PINMUX(70, 0)>,
359				 <PINMUX(71, 0)>,
360				 <PINMUX(72, 0)>,
361				 <PINMUX(73, 0)>;
362			bias-pull-up;
363			drive-strength = <12>;
364			input-enable;
365		};
366	};
367
368	mmc1_pins: mmc1-0 {
369		clk-pins {
370			pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
371					      GPOEN_ENABLE,
372					      GPI_NONE)>;
373			bias-pull-up;
374			drive-strength = <12>;
375			input-disable;
376			input-schmitt-disable;
377			slew-rate = <0>;
378		};
379
380		mmc-pins {
381			pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
382					     GPOEN_SYS_SDIO1_CMD,
383					     GPI_SYS_SDIO1_CMD)>,
384				 <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
385					      GPOEN_SYS_SDIO1_DATA0,
386					      GPI_SYS_SDIO1_DATA0)>,
387				 <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
388					      GPOEN_SYS_SDIO1_DATA1,
389					      GPI_SYS_SDIO1_DATA1)>,
390				 <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
391					     GPOEN_SYS_SDIO1_DATA2,
392					     GPI_SYS_SDIO1_DATA2)>,
393				 <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
394					     GPOEN_SYS_SDIO1_DATA3,
395					     GPI_SYS_SDIO1_DATA3)>;
396			bias-pull-up;
397			drive-strength = <12>;
398			input-enable;
399			input-schmitt-enable;
400			slew-rate = <0>;
401		};
402	};
403
404	spi0_pins: spi0-0 {
405		mosi-pins {
406			pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
407					      GPOEN_ENABLE,
408					      GPI_NONE)>;
409			bias-disable;
410			input-disable;
411			input-schmitt-disable;
412		};
413
414		miso-pins {
415			pinmux = <GPIOMUX(53, GPOUT_LOW,
416					      GPOEN_DISABLE,
417					      GPI_SYS_SPI0_RXD)>;
418			bias-pull-up;
419			input-enable;
420			input-schmitt-enable;
421		};
422
423		sck-pins {
424			pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
425					      GPOEN_ENABLE,
426					      GPI_SYS_SPI0_CLK)>;
427			bias-disable;
428			input-disable;
429			input-schmitt-disable;
430		};
431
432		ss-pins {
433			pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
434					      GPOEN_ENABLE,
435					      GPI_SYS_SPI0_FSS)>;
436			bias-disable;
437			input-disable;
438			input-schmitt-disable;
439		};
440	};
441
442	uart0_pins: uart0-0 {
443		tx-pins {
444			pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
445					     GPOEN_ENABLE,
446					     GPI_NONE)>;
447			bias-disable;
448			drive-strength = <12>;
449			input-disable;
450			input-schmitt-disable;
451			slew-rate = <0>;
452		};
453
454		rx-pins {
455			pinmux = <GPIOMUX(6, GPOUT_LOW,
456					     GPOEN_DISABLE,
457					     GPI_SYS_UART0_RX)>;
458			bias-disable; /* external pull-up */
459			drive-strength = <2>;
460			input-enable;
461			input-schmitt-enable;
462			slew-rate = <0>;
463		};
464	};
465};
466
467&uart0 {
468	pinctrl-names = "default";
469	pinctrl-0 = <&uart0_pins>;
470	status = "okay";
471};
472
473&usb0 {
474	dr_mode = "peripheral";
475	status = "okay";
476};
477
478&U74_1 {
479	cpu-supply = <&vdd_cpu>;
480};
481
482&U74_2 {
483	cpu-supply = <&vdd_cpu>;
484};
485
486&U74_3 {
487	cpu-supply = <&vdd_cpu>;
488};
489
490&U74_4 {
491	cpu-supply = <&vdd_cpu>;
492};
493