1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
5 */
6
7/dts-v1/;
8#include "jh7110.dtsi"
9#include "jh7110-pinfunc.h"
10#include <dt-bindings/gpio/gpio.h>
11
12/ {
13	aliases {
14		ethernet0 = &gmac0;
15		ethernet1 = &gmac1;
16		i2c0 = &i2c0;
17		i2c2 = &i2c2;
18		i2c5 = &i2c5;
19		i2c6 = &i2c6;
20		mmc0 = &mmc0;
21		mmc1 = &mmc1;
22		serial0 = &uart0;
23	};
24
25	chosen {
26		stdout-path = "serial0:115200n8";
27	};
28
29	cpus {
30		timebase-frequency = <4000000>;
31	};
32
33	memory@40000000 {
34		device_type = "memory";
35		reg = <0x0 0x40000000 0x1 0x0>;
36	};
37
38	gpio-restart {
39		compatible = "gpio-restart";
40		gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
41		priority = <224>;
42	};
43};
44
45&dvp_clk {
46	clock-frequency = <74250000>;
47};
48
49&gmac0_rgmii_rxin {
50	clock-frequency = <125000000>;
51};
52
53&gmac0_rmii_refin {
54	clock-frequency = <50000000>;
55};
56
57&gmac1_rgmii_rxin {
58	clock-frequency = <125000000>;
59};
60
61&gmac1_rmii_refin {
62	clock-frequency = <50000000>;
63};
64
65&hdmitx0_pixelclk {
66	clock-frequency = <297000000>;
67};
68
69&i2srx_bclk_ext {
70	clock-frequency = <12288000>;
71};
72
73&i2srx_lrck_ext {
74	clock-frequency = <192000>;
75};
76
77&i2stx_bclk_ext {
78	clock-frequency = <12288000>;
79};
80
81&i2stx_lrck_ext {
82	clock-frequency = <192000>;
83};
84
85&mclk_ext {
86	clock-frequency = <12288000>;
87};
88
89&osc {
90	clock-frequency = <24000000>;
91};
92
93&rtc_osc {
94	clock-frequency = <32768>;
95};
96
97&tdm_ext {
98	clock-frequency = <49152000>;
99};
100
101&gmac0 {
102	phy-handle = <&phy0>;
103	phy-mode = "rgmii-id";
104	status = "okay";
105
106	mdio {
107		#address-cells = <1>;
108		#size-cells = <0>;
109		compatible = "snps,dwmac-mdio";
110
111		phy0: ethernet-phy@0 {
112			reg = <0>;
113		};
114	};
115};
116
117&gmac1 {
118	phy-handle = <&phy1>;
119	phy-mode = "rgmii-id";
120	status = "okay";
121
122	mdio {
123		#address-cells = <1>;
124		#size-cells = <0>;
125		compatible = "snps,dwmac-mdio";
126
127		phy1: ethernet-phy@1 {
128			reg = <0>;
129		};
130	};
131};
132
133&i2c0 {
134	clock-frequency = <100000>;
135	i2c-sda-hold-time-ns = <300>;
136	i2c-sda-falling-time-ns = <510>;
137	i2c-scl-falling-time-ns = <510>;
138	pinctrl-names = "default";
139	pinctrl-0 = <&i2c0_pins>;
140	status = "okay";
141};
142
143&i2c2 {
144	clock-frequency = <100000>;
145	i2c-sda-hold-time-ns = <300>;
146	i2c-sda-falling-time-ns = <510>;
147	i2c-scl-falling-time-ns = <510>;
148	pinctrl-names = "default";
149	pinctrl-0 = <&i2c2_pins>;
150	status = "okay";
151};
152
153&i2c5 {
154	clock-frequency = <100000>;
155	i2c-sda-hold-time-ns = <300>;
156	i2c-sda-falling-time-ns = <510>;
157	i2c-scl-falling-time-ns = <510>;
158	pinctrl-names = "default";
159	pinctrl-0 = <&i2c5_pins>;
160	status = "okay";
161
162	axp15060: pmic@36 {
163		compatible = "x-powers,axp15060";
164		reg = <0x36>;
165		interrupts = <0>;
166		interrupt-controller;
167		#interrupt-cells = <1>;
168
169		regulators {
170			vcc_3v3: dcdc1 {
171				regulator-boot-on;
172				regulator-always-on;
173				regulator-min-microvolt = <3300000>;
174				regulator-max-microvolt = <3300000>;
175				regulator-name = "vcc_3v3";
176			};
177
178			vdd_cpu: dcdc2 {
179				regulator-always-on;
180				regulator-min-microvolt = <500000>;
181				regulator-max-microvolt = <1540000>;
182				regulator-name = "vdd-cpu";
183			};
184
185			emmc_vdd: aldo4 {
186				regulator-boot-on;
187				regulator-always-on;
188				regulator-min-microvolt = <1800000>;
189				regulator-max-microvolt = <1800000>;
190				regulator-name = "emmc_vdd";
191			};
192		};
193	};
194};
195
196&i2c6 {
197	clock-frequency = <100000>;
198	i2c-sda-hold-time-ns = <300>;
199	i2c-sda-falling-time-ns = <510>;
200	i2c-scl-falling-time-ns = <510>;
201	pinctrl-names = "default";
202	pinctrl-0 = <&i2c6_pins>;
203	status = "okay";
204};
205
206&mmc0 {
207	max-frequency = <100000000>;
208	bus-width = <8>;
209	cap-mmc-highspeed;
210	mmc-ddr-1_8v;
211	mmc-hs200-1_8v;
212	non-removable;
213	cap-mmc-hw-reset;
214	post-power-on-delay-ms = <200>;
215	pinctrl-names = "default";
216	pinctrl-0 = <&mmc0_pins>;
217	vmmc-supply = <&vcc_3v3>;
218	vqmmc-supply = <&emmc_vdd>;
219	status = "okay";
220};
221
222&mmc1 {
223	max-frequency = <100000000>;
224	bus-width = <4>;
225	no-sdio;
226	no-mmc;
227	broken-cd;
228	cap-sd-highspeed;
229	post-power-on-delay-ms = <200>;
230	pinctrl-names = "default";
231	pinctrl-0 = <&mmc1_pins>;
232	status = "okay";
233};
234
235&qspi {
236	#address-cells = <1>;
237	#size-cells = <0>;
238	status = "okay";
239
240	nor_flash: flash@0 {
241		compatible = "jedec,spi-nor";
242		reg = <0>;
243		cdns,read-delay = <5>;
244		spi-max-frequency = <12000000>;
245		cdns,tshsl-ns = <1>;
246		cdns,tsd2d-ns = <1>;
247		cdns,tchsh-ns = <1>;
248		cdns,tslch-ns = <1>;
249
250		partitions {
251			compatible = "fixed-partitions";
252			#address-cells = <1>;
253			#size-cells = <1>;
254
255			spl@0 {
256				reg = <0x0 0x80000>;
257			};
258			uboot-env@f0000 {
259				reg = <0xf0000 0x10000>;
260			};
261			uboot@100000 {
262				reg = <0x100000 0x400000>;
263			};
264			reserved-data@600000 {
265				reg = <0x600000 0xa00000>;
266			};
267		};
268	};
269};
270
271&spi0 {
272	pinctrl-names = "default";
273	pinctrl-0 = <&spi0_pins>;
274	status = "okay";
275
276	spi_dev0: spi@0 {
277		compatible = "rohm,dh2228fv";
278		reg = <0>;
279		spi-max-frequency = <10000000>;
280	};
281};
282
283&sysgpio {
284	i2c0_pins: i2c0-0 {
285		i2c-pins {
286			pinmux = <GPIOMUX(57, GPOUT_LOW,
287					      GPOEN_SYS_I2C0_CLK,
288					      GPI_SYS_I2C0_CLK)>,
289				 <GPIOMUX(58, GPOUT_LOW,
290					      GPOEN_SYS_I2C0_DATA,
291					      GPI_SYS_I2C0_DATA)>;
292			bias-disable; /* external pull-up */
293			input-enable;
294			input-schmitt-enable;
295		};
296	};
297
298	i2c2_pins: i2c2-0 {
299		i2c-pins {
300			pinmux = <GPIOMUX(3, GPOUT_LOW,
301					     GPOEN_SYS_I2C2_CLK,
302					     GPI_SYS_I2C2_CLK)>,
303				 <GPIOMUX(2, GPOUT_LOW,
304					     GPOEN_SYS_I2C2_DATA,
305					     GPI_SYS_I2C2_DATA)>;
306			bias-disable; /* external pull-up */
307			input-enable;
308			input-schmitt-enable;
309		};
310	};
311
312	i2c5_pins: i2c5-0 {
313		i2c-pins {
314			pinmux = <GPIOMUX(19, GPOUT_LOW,
315					      GPOEN_SYS_I2C5_CLK,
316					      GPI_SYS_I2C5_CLK)>,
317				 <GPIOMUX(20, GPOUT_LOW,
318					      GPOEN_SYS_I2C5_DATA,
319					      GPI_SYS_I2C5_DATA)>;
320			bias-disable; /* external pull-up */
321			input-enable;
322			input-schmitt-enable;
323		};
324	};
325
326	i2c6_pins: i2c6-0 {
327		i2c-pins {
328			pinmux = <GPIOMUX(16, GPOUT_LOW,
329					      GPOEN_SYS_I2C6_CLK,
330					      GPI_SYS_I2C6_CLK)>,
331				 <GPIOMUX(17, GPOUT_LOW,
332					      GPOEN_SYS_I2C6_DATA,
333					      GPI_SYS_I2C6_DATA)>;
334			bias-disable; /* external pull-up */
335			input-enable;
336			input-schmitt-enable;
337		};
338	};
339
340	mmc0_pins: mmc0-0 {
341		 rst-pins {
342			pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
343					      GPOEN_ENABLE,
344					      GPI_NONE)>;
345			bias-pull-up;
346			drive-strength = <12>;
347			input-disable;
348			input-schmitt-disable;
349			slew-rate = <0>;
350		};
351
352		mmc-pins {
353			pinmux = <PINMUX(64, 0)>,
354				 <PINMUX(65, 0)>,
355				 <PINMUX(66, 0)>,
356				 <PINMUX(67, 0)>,
357				 <PINMUX(68, 0)>,
358				 <PINMUX(69, 0)>,
359				 <PINMUX(70, 0)>,
360				 <PINMUX(71, 0)>,
361				 <PINMUX(72, 0)>,
362				 <PINMUX(73, 0)>;
363			bias-pull-up;
364			drive-strength = <12>;
365			input-enable;
366		};
367	};
368
369	mmc1_pins: mmc1-0 {
370		clk-pins {
371			pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
372					      GPOEN_ENABLE,
373					      GPI_NONE)>;
374			bias-pull-up;
375			drive-strength = <12>;
376			input-disable;
377			input-schmitt-disable;
378			slew-rate = <0>;
379		};
380
381		mmc-pins {
382			pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
383					     GPOEN_SYS_SDIO1_CMD,
384					     GPI_SYS_SDIO1_CMD)>,
385				 <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
386					      GPOEN_SYS_SDIO1_DATA0,
387					      GPI_SYS_SDIO1_DATA0)>,
388				 <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
389					      GPOEN_SYS_SDIO1_DATA1,
390					      GPI_SYS_SDIO1_DATA1)>,
391				 <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
392					     GPOEN_SYS_SDIO1_DATA2,
393					     GPI_SYS_SDIO1_DATA2)>,
394				 <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
395					     GPOEN_SYS_SDIO1_DATA3,
396					     GPI_SYS_SDIO1_DATA3)>;
397			bias-pull-up;
398			drive-strength = <12>;
399			input-enable;
400			input-schmitt-enable;
401			slew-rate = <0>;
402		};
403	};
404
405	spi0_pins: spi0-0 {
406		mosi-pins {
407			pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
408					      GPOEN_ENABLE,
409					      GPI_NONE)>;
410			bias-disable;
411			input-disable;
412			input-schmitt-disable;
413		};
414
415		miso-pins {
416			pinmux = <GPIOMUX(53, GPOUT_LOW,
417					      GPOEN_DISABLE,
418					      GPI_SYS_SPI0_RXD)>;
419			bias-pull-up;
420			input-enable;
421			input-schmitt-enable;
422		};
423
424		sck-pins {
425			pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
426					      GPOEN_ENABLE,
427					      GPI_SYS_SPI0_CLK)>;
428			bias-disable;
429			input-disable;
430			input-schmitt-disable;
431		};
432
433		ss-pins {
434			pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
435					      GPOEN_ENABLE,
436					      GPI_SYS_SPI0_FSS)>;
437			bias-disable;
438			input-disable;
439			input-schmitt-disable;
440		};
441	};
442
443	uart0_pins: uart0-0 {
444		tx-pins {
445			pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
446					     GPOEN_ENABLE,
447					     GPI_NONE)>;
448			bias-disable;
449			drive-strength = <12>;
450			input-disable;
451			input-schmitt-disable;
452			slew-rate = <0>;
453		};
454
455		rx-pins {
456			pinmux = <GPIOMUX(6, GPOUT_LOW,
457					     GPOEN_DISABLE,
458					     GPI_SYS_UART0_RX)>;
459			bias-disable; /* external pull-up */
460			drive-strength = <2>;
461			input-enable;
462			input-schmitt-enable;
463			slew-rate = <0>;
464		};
465	};
466};
467
468&uart0 {
469	pinctrl-names = "default";
470	pinctrl-0 = <&uart0_pins>;
471	status = "okay";
472};
473
474&usb0 {
475	dr_mode = "peripheral";
476	status = "okay";
477};
478
479&U74_1 {
480	cpu-supply = <&vdd_cpu>;
481};
482
483&U74_2 {
484	cpu-supply = <&vdd_cpu>;
485};
486
487&U74_3 {
488	cpu-supply = <&vdd_cpu>;
489};
490
491&U74_4 {
492	cpu-supply = <&vdd_cpu>;
493};
494