1*e22f09e5SJianlong Huang /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2*e22f09e5SJianlong Huang /* 3*e22f09e5SJianlong Huang * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> 4*e22f09e5SJianlong Huang * Copyright (C) 2022 StarFive Technology Co., Ltd. 5*e22f09e5SJianlong Huang */ 6*e22f09e5SJianlong Huang 7*e22f09e5SJianlong Huang #ifndef __JH7110_PINFUNC_H__ 8*e22f09e5SJianlong Huang #define __JH7110_PINFUNC_H__ 9*e22f09e5SJianlong Huang 10*e22f09e5SJianlong Huang /* 11*e22f09e5SJianlong Huang * mux bits: 12*e22f09e5SJianlong Huang * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 | 13*e22f09e5SJianlong Huang * | din | dout | doen | function | gpio nr | 14*e22f09e5SJianlong Huang * 15*e22f09e5SJianlong Huang * dout: output signal 16*e22f09e5SJianlong Huang * doen: output enable signal 17*e22f09e5SJianlong Huang * din: optional input signal, 0xff = none 18*e22f09e5SJianlong Huang * function: function selector 19*e22f09e5SJianlong Huang * gpio nr: gpio number, 0 - 63 20*e22f09e5SJianlong Huang */ 21*e22f09e5SJianlong Huang #define GPIOMUX(n, dout, doen, din) ( \ 22*e22f09e5SJianlong Huang (((din) & 0xff) << 24) | \ 23*e22f09e5SJianlong Huang (((dout) & 0xff) << 16) | \ 24*e22f09e5SJianlong Huang (((doen) & 0x3f) << 10) | \ 25*e22f09e5SJianlong Huang ((n) & 0x3f)) 26*e22f09e5SJianlong Huang 27*e22f09e5SJianlong Huang #define PINMUX(n, func) ((1 << 10) | (((func) & 0x3) << 8) | ((n) & 0xff)) 28*e22f09e5SJianlong Huang 29*e22f09e5SJianlong Huang /* sys_iomux dout */ 30*e22f09e5SJianlong Huang #define GPOUT_LOW 0 31*e22f09e5SJianlong Huang #define GPOUT_HIGH 1 32*e22f09e5SJianlong Huang #define GPOUT_SYS_WAVE511_UART_TX 2 33*e22f09e5SJianlong Huang #define GPOUT_SYS_CAN0_STBY 3 34*e22f09e5SJianlong Huang #define GPOUT_SYS_CAN0_TST_NEXT_BIT 4 35*e22f09e5SJianlong Huang #define GPOUT_SYS_CAN0_TST_SAMPLE_POINT 5 36*e22f09e5SJianlong Huang #define GPOUT_SYS_CAN0_TXD 6 37*e22f09e5SJianlong Huang #define GPOUT_SYS_USB_DRIVE_VBUS 7 38*e22f09e5SJianlong Huang #define GPOUT_SYS_QSPI_CS1 8 39*e22f09e5SJianlong Huang #define GPOUT_SYS_SPDIF 9 40*e22f09e5SJianlong Huang #define GPOUT_SYS_HDMI_CEC_SDA 10 41*e22f09e5SJianlong Huang #define GPOUT_SYS_HDMI_DDC_SCL 11 42*e22f09e5SJianlong Huang #define GPOUT_SYS_HDMI_DDC_SDA 12 43*e22f09e5SJianlong Huang #define GPOUT_SYS_WATCHDOG 13 44*e22f09e5SJianlong Huang #define GPOUT_SYS_I2C0_CLK 14 45*e22f09e5SJianlong Huang #define GPOUT_SYS_I2C0_DATA 15 46*e22f09e5SJianlong Huang #define GPOUT_SYS_SDIO0_BACK_END_POWER 16 47*e22f09e5SJianlong Huang #define GPOUT_SYS_SDIO0_CARD_POWER_EN 17 48*e22f09e5SJianlong Huang #define GPOUT_SYS_SDIO0_CCMD_OD_PULLUP_EN 18 49*e22f09e5SJianlong Huang #define GPOUT_SYS_SDIO0_RST 19 50*e22f09e5SJianlong Huang #define GPOUT_SYS_UART0_TX 20 51*e22f09e5SJianlong Huang #define GPOUT_SYS_HIFI4_JTAG_TDO 21 52*e22f09e5SJianlong Huang #define GPOUT_SYS_JTAG_TDO 22 53*e22f09e5SJianlong Huang #define GPOUT_SYS_PDM_MCLK 23 54*e22f09e5SJianlong Huang #define GPOUT_SYS_PWM_CHANNEL0 24 55*e22f09e5SJianlong Huang #define GPOUT_SYS_PWM_CHANNEL1 25 56*e22f09e5SJianlong Huang #define GPOUT_SYS_PWM_CHANNEL2 26 57*e22f09e5SJianlong Huang #define GPOUT_SYS_PWM_CHANNEL3 27 58*e22f09e5SJianlong Huang #define GPOUT_SYS_PWMDAC_LEFT 28 59*e22f09e5SJianlong Huang #define GPOUT_SYS_PWMDAC_RIGHT 29 60*e22f09e5SJianlong Huang #define GPOUT_SYS_SPI0_CLK 30 61*e22f09e5SJianlong Huang #define GPOUT_SYS_SPI0_FSS 31 62*e22f09e5SJianlong Huang #define GPOUT_SYS_SPI0_TXD 32 63*e22f09e5SJianlong Huang #define GPOUT_SYS_GMAC_PHYCLK 33 64*e22f09e5SJianlong Huang #define GPOUT_SYS_I2SRX_BCLK 34 65*e22f09e5SJianlong Huang #define GPOUT_SYS_I2SRX_LRCK 35 66*e22f09e5SJianlong Huang #define GPOUT_SYS_I2STX0_BCLK 36 67*e22f09e5SJianlong Huang #define GPOUT_SYS_I2STX0_LRCK 37 68*e22f09e5SJianlong Huang #define GPOUT_SYS_MCLK 38 69*e22f09e5SJianlong Huang #define GPOUT_SYS_TDM_CLK 39 70*e22f09e5SJianlong Huang #define GPOUT_SYS_TDM_SYNC 40 71*e22f09e5SJianlong Huang #define GPOUT_SYS_TDM_TXD 41 72*e22f09e5SJianlong Huang #define GPOUT_SYS_TRACE_DATA0 42 73*e22f09e5SJianlong Huang #define GPOUT_SYS_TRACE_DATA1 43 74*e22f09e5SJianlong Huang #define GPOUT_SYS_TRACE_DATA2 44 75*e22f09e5SJianlong Huang #define GPOUT_SYS_TRACE_DATA3 45 76*e22f09e5SJianlong Huang #define GPOUT_SYS_TRACE_REF 46 77*e22f09e5SJianlong Huang #define GPOUT_SYS_CAN1_STBY 47 78*e22f09e5SJianlong Huang #define GPOUT_SYS_CAN1_TST_NEXT_BIT 48 79*e22f09e5SJianlong Huang #define GPOUT_SYS_CAN1_TST_SAMPLE_POINT 49 80*e22f09e5SJianlong Huang #define GPOUT_SYS_CAN1_TXD 50 81*e22f09e5SJianlong Huang #define GPOUT_SYS_I2C1_CLK 51 82*e22f09e5SJianlong Huang #define GPOUT_SYS_I2C1_DATA 52 83*e22f09e5SJianlong Huang #define GPOUT_SYS_SDIO1_BACK_END_POWER 53 84*e22f09e5SJianlong Huang #define GPOUT_SYS_SDIO1_CARD_POWER_EN 54 85*e22f09e5SJianlong Huang #define GPOUT_SYS_SDIO1_CLK 55 86*e22f09e5SJianlong Huang #define GPOUT_SYS_SDIO1_CMD_OD_PULLUP_EN 56 87*e22f09e5SJianlong Huang #define GPOUT_SYS_SDIO1_CMD 57 88*e22f09e5SJianlong Huang #define GPOUT_SYS_SDIO1_DATA0 58 89*e22f09e5SJianlong Huang #define GPOUT_SYS_SDIO1_DATA1 59 90*e22f09e5SJianlong Huang #define GPOUT_SYS_SDIO1_DATA2 60 91*e22f09e5SJianlong Huang #define GPOUT_SYS_SDIO1_DATA3 61 92*e22f09e5SJianlong Huang #define GPOUT_SYS_SDIO1_DATA4 63 93*e22f09e5SJianlong Huang #define GPOUT_SYS_SDIO1_DATA5 63 94*e22f09e5SJianlong Huang #define GPOUT_SYS_SDIO1_DATA6 64 95*e22f09e5SJianlong Huang #define GPOUT_SYS_SDIO1_DATA7 65 96*e22f09e5SJianlong Huang #define GPOUT_SYS_SDIO1_RST 66 97*e22f09e5SJianlong Huang #define GPOUT_SYS_UART1_RTS 67 98*e22f09e5SJianlong Huang #define GPOUT_SYS_UART1_TX 68 99*e22f09e5SJianlong Huang #define GPOUT_SYS_I2STX1_SDO0 69 100*e22f09e5SJianlong Huang #define GPOUT_SYS_I2STX1_SDO1 70 101*e22f09e5SJianlong Huang #define GPOUT_SYS_I2STX1_SDO2 71 102*e22f09e5SJianlong Huang #define GPOUT_SYS_I2STX1_SDO3 72 103*e22f09e5SJianlong Huang #define GPOUT_SYS_SPI1_CLK 73 104*e22f09e5SJianlong Huang #define GPOUT_SYS_SPI1_FSS 74 105*e22f09e5SJianlong Huang #define GPOUT_SYS_SPI1_TXD 75 106*e22f09e5SJianlong Huang #define GPOUT_SYS_I2C2_CLK 76 107*e22f09e5SJianlong Huang #define GPOUT_SYS_I2C2_DATA 77 108*e22f09e5SJianlong Huang #define GPOUT_SYS_UART2_RTS 78 109*e22f09e5SJianlong Huang #define GPOUT_SYS_UART2_TX 79 110*e22f09e5SJianlong Huang #define GPOUT_SYS_SPI2_CLK 80 111*e22f09e5SJianlong Huang #define GPOUT_SYS_SPI2_FSS 81 112*e22f09e5SJianlong Huang #define GPOUT_SYS_SPI2_TXD 82 113*e22f09e5SJianlong Huang #define GPOUT_SYS_I2C3_CLK 83 114*e22f09e5SJianlong Huang #define GPOUT_SYS_I2C3_DATA 84 115*e22f09e5SJianlong Huang #define GPOUT_SYS_UART3_TX 85 116*e22f09e5SJianlong Huang #define GPOUT_SYS_SPI3_CLK 86 117*e22f09e5SJianlong Huang #define GPOUT_SYS_SPI3_FSS 87 118*e22f09e5SJianlong Huang #define GPOUT_SYS_SPI3_TXD 88 119*e22f09e5SJianlong Huang #define GPOUT_SYS_I2C4_CLK 89 120*e22f09e5SJianlong Huang #define GPOUT_SYS_I2C4_DATA 90 121*e22f09e5SJianlong Huang #define GPOUT_SYS_UART4_RTS 91 122*e22f09e5SJianlong Huang #define GPOUT_SYS_UART4_TX 92 123*e22f09e5SJianlong Huang #define GPOUT_SYS_SPI4_CLK 93 124*e22f09e5SJianlong Huang #define GPOUT_SYS_SPI4_FSS 94 125*e22f09e5SJianlong Huang #define GPOUT_SYS_SPI4_TXD 95 126*e22f09e5SJianlong Huang #define GPOUT_SYS_I2C5_CLK 96 127*e22f09e5SJianlong Huang #define GPOUT_SYS_I2C5_DATA 97 128*e22f09e5SJianlong Huang #define GPOUT_SYS_UART5_RTS 98 129*e22f09e5SJianlong Huang #define GPOUT_SYS_UART5_TX 99 130*e22f09e5SJianlong Huang #define GPOUT_SYS_SPI5_CLK 100 131*e22f09e5SJianlong Huang #define GPOUT_SYS_SPI5_FSS 101 132*e22f09e5SJianlong Huang #define GPOUT_SYS_SPI5_TXD 102 133*e22f09e5SJianlong Huang #define GPOUT_SYS_I2C6_CLK 103 134*e22f09e5SJianlong Huang #define GPOUT_SYS_I2C6_DATA 104 135*e22f09e5SJianlong Huang #define GPOUT_SYS_SPI6_CLK 105 136*e22f09e5SJianlong Huang #define GPOUT_SYS_SPI6_FSS 106 137*e22f09e5SJianlong Huang #define GPOUT_SYS_SPI6_TXD 107 138*e22f09e5SJianlong Huang 139*e22f09e5SJianlong Huang /* aon_iomux dout */ 140*e22f09e5SJianlong Huang #define GPOUT_AON_CLK_32K_OUT 2 141*e22f09e5SJianlong Huang #define GPOUT_AON_PTC0_PWM4 3 142*e22f09e5SJianlong Huang #define GPOUT_AON_PTC0_PWM5 4 143*e22f09e5SJianlong Huang #define GPOUT_AON_PTC0_PWM6 5 144*e22f09e5SJianlong Huang #define GPOUT_AON_PTC0_PWM7 6 145*e22f09e5SJianlong Huang #define GPOUT_AON_CLK_GCLK0 7 146*e22f09e5SJianlong Huang #define GPOUT_AON_CLK_GCLK1 8 147*e22f09e5SJianlong Huang #define GPOUT_AON_CLK_GCLK2 9 148*e22f09e5SJianlong Huang 149*e22f09e5SJianlong Huang /* sys_iomux doen */ 150*e22f09e5SJianlong Huang #define GPOEN_ENABLE 0 151*e22f09e5SJianlong Huang #define GPOEN_DISABLE 1 152*e22f09e5SJianlong Huang #define GPOEN_SYS_HDMI_CEC_SDA 2 153*e22f09e5SJianlong Huang #define GPOEN_SYS_HDMI_DDC_SCL 3 154*e22f09e5SJianlong Huang #define GPOEN_SYS_HDMI_DDC_SDA 4 155*e22f09e5SJianlong Huang #define GPOEN_SYS_I2C0_CLK 5 156*e22f09e5SJianlong Huang #define GPOEN_SYS_I2C0_DATA 6 157*e22f09e5SJianlong Huang #define GPOEN_SYS_HIFI4_JTAG_TDO 7 158*e22f09e5SJianlong Huang #define GPOEN_SYS_JTAG_TDO 8 159*e22f09e5SJianlong Huang #define GPOEN_SYS_PWM0_CHANNEL0 9 160*e22f09e5SJianlong Huang #define GPOEN_SYS_PWM0_CHANNEL1 10 161*e22f09e5SJianlong Huang #define GPOEN_SYS_PWM0_CHANNEL2 11 162*e22f09e5SJianlong Huang #define GPOEN_SYS_PWM0_CHANNEL3 12 163*e22f09e5SJianlong Huang #define GPOEN_SYS_SPI0_NSSPCTL 13 164*e22f09e5SJianlong Huang #define GPOEN_SYS_SPI0_NSSP 14 165*e22f09e5SJianlong Huang #define GPOEN_SYS_TDM_SYNC 15 166*e22f09e5SJianlong Huang #define GPOEN_SYS_TDM_TXD 16 167*e22f09e5SJianlong Huang #define GPOEN_SYS_I2C1_CLK 17 168*e22f09e5SJianlong Huang #define GPOEN_SYS_I2C1_DATA 18 169*e22f09e5SJianlong Huang #define GPOEN_SYS_SDIO1_CMD 19 170*e22f09e5SJianlong Huang #define GPOEN_SYS_SDIO1_DATA0 20 171*e22f09e5SJianlong Huang #define GPOEN_SYS_SDIO1_DATA1 21 172*e22f09e5SJianlong Huang #define GPOEN_SYS_SDIO1_DATA2 22 173*e22f09e5SJianlong Huang #define GPOEN_SYS_SDIO1_DATA3 23 174*e22f09e5SJianlong Huang #define GPOEN_SYS_SDIO1_DATA4 24 175*e22f09e5SJianlong Huang #define GPOEN_SYS_SDIO1_DATA5 25 176*e22f09e5SJianlong Huang #define GPOEN_SYS_SDIO1_DATA6 26 177*e22f09e5SJianlong Huang #define GPOEN_SYS_SDIO1_DATA7 27 178*e22f09e5SJianlong Huang #define GPOEN_SYS_SPI1_NSSPCTL 28 179*e22f09e5SJianlong Huang #define GPOEN_SYS_SPI1_NSSP 29 180*e22f09e5SJianlong Huang #define GPOEN_SYS_I2C2_CLK 30 181*e22f09e5SJianlong Huang #define GPOEN_SYS_I2C2_DATA 31 182*e22f09e5SJianlong Huang #define GPOEN_SYS_SPI2_NSSPCTL 32 183*e22f09e5SJianlong Huang #define GPOEN_SYS_SPI2_NSSP 33 184*e22f09e5SJianlong Huang #define GPOEN_SYS_I2C3_CLK 34 185*e22f09e5SJianlong Huang #define GPOEN_SYS_I2C3_DATA 35 186*e22f09e5SJianlong Huang #define GPOEN_SYS_SPI3_NSSPCTL 36 187*e22f09e5SJianlong Huang #define GPOEN_SYS_SPI3_NSSP 37 188*e22f09e5SJianlong Huang #define GPOEN_SYS_I2C4_CLK 38 189*e22f09e5SJianlong Huang #define GPOEN_SYS_I2C4_DATA 39 190*e22f09e5SJianlong Huang #define GPOEN_SYS_SPI4_NSSPCTL 40 191*e22f09e5SJianlong Huang #define GPOEN_SYS_SPI4_NSSP 41 192*e22f09e5SJianlong Huang #define GPOEN_SYS_I2C5_CLK 42 193*e22f09e5SJianlong Huang #define GPOEN_SYS_I2C5_DATA 43 194*e22f09e5SJianlong Huang #define GPOEN_SYS_SPI5_NSSPCTL 44 195*e22f09e5SJianlong Huang #define GPOEN_SYS_SPI5_NSSP 45 196*e22f09e5SJianlong Huang #define GPOEN_SYS_I2C6_CLK 46 197*e22f09e5SJianlong Huang #define GPOEN_SYS_I2C6_DATA 47 198*e22f09e5SJianlong Huang #define GPOEN_SYS_SPI6_NSSPCTL 48 199*e22f09e5SJianlong Huang #define GPOEN_SYS_SPI6_NSSP 49 200*e22f09e5SJianlong Huang 201*e22f09e5SJianlong Huang /* aon_iomux doen */ 202*e22f09e5SJianlong Huang #define GPOEN_AON_PTC0_OE_N_4 2 203*e22f09e5SJianlong Huang #define GPOEN_AON_PTC0_OE_N_5 3 204*e22f09e5SJianlong Huang #define GPOEN_AON_PTC0_OE_N_6 4 205*e22f09e5SJianlong Huang #define GPOEN_AON_PTC0_OE_N_7 5 206*e22f09e5SJianlong Huang 207*e22f09e5SJianlong Huang /* sys_iomux gin */ 208*e22f09e5SJianlong Huang #define GPI_NONE 255 209*e22f09e5SJianlong Huang 210*e22f09e5SJianlong Huang #define GPI_SYS_WAVE511_UART_RX 0 211*e22f09e5SJianlong Huang #define GPI_SYS_CAN0_RXD 1 212*e22f09e5SJianlong Huang #define GPI_SYS_USB_OVERCURRENT 2 213*e22f09e5SJianlong Huang #define GPI_SYS_SPDIF 3 214*e22f09e5SJianlong Huang #define GPI_SYS_JTAG_RST 4 215*e22f09e5SJianlong Huang #define GPI_SYS_HDMI_CEC_SDA 5 216*e22f09e5SJianlong Huang #define GPI_SYS_HDMI_DDC_SCL 6 217*e22f09e5SJianlong Huang #define GPI_SYS_HDMI_DDC_SDA 7 218*e22f09e5SJianlong Huang #define GPI_SYS_HDMI_HPD 8 219*e22f09e5SJianlong Huang #define GPI_SYS_I2C0_CLK 9 220*e22f09e5SJianlong Huang #define GPI_SYS_I2C0_DATA 10 221*e22f09e5SJianlong Huang #define GPI_SYS_SDIO0_CD 11 222*e22f09e5SJianlong Huang #define GPI_SYS_SDIO0_INT 12 223*e22f09e5SJianlong Huang #define GPI_SYS_SDIO0_WP 13 224*e22f09e5SJianlong Huang #define GPI_SYS_UART0_RX 14 225*e22f09e5SJianlong Huang #define GPI_SYS_HIFI4_JTAG_TCK 15 226*e22f09e5SJianlong Huang #define GPI_SYS_HIFI4_JTAG_TDI 16 227*e22f09e5SJianlong Huang #define GPI_SYS_HIFI4_JTAG_TMS 17 228*e22f09e5SJianlong Huang #define GPI_SYS_HIFI4_JTAG_RST 18 229*e22f09e5SJianlong Huang #define GPI_SYS_JTAG_TDI 19 230*e22f09e5SJianlong Huang #define GPI_SYS_JTAG_TMS 20 231*e22f09e5SJianlong Huang #define GPI_SYS_PDM_DMIC0 21 232*e22f09e5SJianlong Huang #define GPI_SYS_PDM_DMIC1 22 233*e22f09e5SJianlong Huang #define GPI_SYS_I2SRX_SDIN0 23 234*e22f09e5SJianlong Huang #define GPI_SYS_I2SRX_SDIN1 24 235*e22f09e5SJianlong Huang #define GPI_SYS_I2SRX_SDIN2 25 236*e22f09e5SJianlong Huang #define GPI_SYS_SPI0_CLK 26 237*e22f09e5SJianlong Huang #define GPI_SYS_SPI0_FSS 27 238*e22f09e5SJianlong Huang #define GPI_SYS_SPI0_RXD 28 239*e22f09e5SJianlong Huang #define GPI_SYS_JTAG_TCK 29 240*e22f09e5SJianlong Huang #define GPI_SYS_MCLK_EXT 30 241*e22f09e5SJianlong Huang #define GPI_SYS_I2SRX_BCLK 31 242*e22f09e5SJianlong Huang #define GPI_SYS_I2SRX_LRCK 32 243*e22f09e5SJianlong Huang #define GPI_SYS_I2STX0_BCLK 33 244*e22f09e5SJianlong Huang #define GPI_SYS_I2STX0_LRCK 34 245*e22f09e5SJianlong Huang #define GPI_SYS_TDM_CLK 35 246*e22f09e5SJianlong Huang #define GPI_SYS_TDM_RXD 36 247*e22f09e5SJianlong Huang #define GPI_SYS_TDM_SYNC 37 248*e22f09e5SJianlong Huang #define GPI_SYS_CAN1_RXD 38 249*e22f09e5SJianlong Huang #define GPI_SYS_I2C1_CLK 39 250*e22f09e5SJianlong Huang #define GPI_SYS_I2C1_DATA 40 251*e22f09e5SJianlong Huang #define GPI_SYS_SDIO1_CD 41 252*e22f09e5SJianlong Huang #define GPI_SYS_SDIO1_INT 42 253*e22f09e5SJianlong Huang #define GPI_SYS_SDIO1_WP 43 254*e22f09e5SJianlong Huang #define GPI_SYS_SDIO1_CMD 44 255*e22f09e5SJianlong Huang #define GPI_SYS_SDIO1_DATA0 45 256*e22f09e5SJianlong Huang #define GPI_SYS_SDIO1_DATA1 46 257*e22f09e5SJianlong Huang #define GPI_SYS_SDIO1_DATA2 47 258*e22f09e5SJianlong Huang #define GPI_SYS_SDIO1_DATA3 48 259*e22f09e5SJianlong Huang #define GPI_SYS_SDIO1_DATA4 49 260*e22f09e5SJianlong Huang #define GPI_SYS_SDIO1_DATA5 50 261*e22f09e5SJianlong Huang #define GPI_SYS_SDIO1_DATA6 51 262*e22f09e5SJianlong Huang #define GPI_SYS_SDIO1_DATA7 52 263*e22f09e5SJianlong Huang #define GPI_SYS_SDIO1_STRB 53 264*e22f09e5SJianlong Huang #define GPI_SYS_UART1_CTS 54 265*e22f09e5SJianlong Huang #define GPI_SYS_UART1_RX 55 266*e22f09e5SJianlong Huang #define GPI_SYS_SPI1_CLK 56 267*e22f09e5SJianlong Huang #define GPI_SYS_SPI1_FSS 57 268*e22f09e5SJianlong Huang #define GPI_SYS_SPI1_RXD 58 269*e22f09e5SJianlong Huang #define GPI_SYS_I2C2_CLK 59 270*e22f09e5SJianlong Huang #define GPI_SYS_I2C2_DATA 60 271*e22f09e5SJianlong Huang #define GPI_SYS_UART2_CTS 61 272*e22f09e5SJianlong Huang #define GPI_SYS_UART2_RX 62 273*e22f09e5SJianlong Huang #define GPI_SYS_SPI2_CLK 63 274*e22f09e5SJianlong Huang #define GPI_SYS_SPI2_FSS 64 275*e22f09e5SJianlong Huang #define GPI_SYS_SPI2_RXD 65 276*e22f09e5SJianlong Huang #define GPI_SYS_I2C3_CLK 66 277*e22f09e5SJianlong Huang #define GPI_SYS_I2C3_DATA 67 278*e22f09e5SJianlong Huang #define GPI_SYS_UART3_RX 68 279*e22f09e5SJianlong Huang #define GPI_SYS_SPI3_CLK 69 280*e22f09e5SJianlong Huang #define GPI_SYS_SPI3_FSS 70 281*e22f09e5SJianlong Huang #define GPI_SYS_SPI3_RXD 71 282*e22f09e5SJianlong Huang #define GPI_SYS_I2C4_CLK 72 283*e22f09e5SJianlong Huang #define GPI_SYS_I2C4_DATA 73 284*e22f09e5SJianlong Huang #define GPI_SYS_UART4_CTS 74 285*e22f09e5SJianlong Huang #define GPI_SYS_UART4_RX 75 286*e22f09e5SJianlong Huang #define GPI_SYS_SPI4_CLK 76 287*e22f09e5SJianlong Huang #define GPI_SYS_SPI4_FSS 77 288*e22f09e5SJianlong Huang #define GPI_SYS_SPI4_RXD 78 289*e22f09e5SJianlong Huang #define GPI_SYS_I2C5_CLK 79 290*e22f09e5SJianlong Huang #define GPI_SYS_I2C5_DATA 80 291*e22f09e5SJianlong Huang #define GPI_SYS_UART5_CTS 81 292*e22f09e5SJianlong Huang #define GPI_SYS_UART5_RX 82 293*e22f09e5SJianlong Huang #define GPI_SYS_SPI5_CLK 83 294*e22f09e5SJianlong Huang #define GPI_SYS_SPI5_FSS 84 295*e22f09e5SJianlong Huang #define GPI_SYS_SPI5_RXD 85 296*e22f09e5SJianlong Huang #define GPI_SYS_I2C6_CLK 86 297*e22f09e5SJianlong Huang #define GPI_SYS_I2C6_DATA 87 298*e22f09e5SJianlong Huang #define GPI_SYS_SPI6_CLK 88 299*e22f09e5SJianlong Huang #define GPI_SYS_SPI6_FSS 89 300*e22f09e5SJianlong Huang #define GPI_SYS_SPI6_RXD 90 301*e22f09e5SJianlong Huang 302*e22f09e5SJianlong Huang /* aon_iomux gin */ 303*e22f09e5SJianlong Huang #define GPI_AON_PMU_GPIO_WAKEUP_0 0 304*e22f09e5SJianlong Huang #define GPI_AON_PMU_GPIO_WAKEUP_1 1 305*e22f09e5SJianlong Huang #define GPI_AON_PMU_GPIO_WAKEUP_2 2 306*e22f09e5SJianlong Huang #define GPI_AON_PMU_GPIO_WAKEUP_3 3 307*e22f09e5SJianlong Huang 308*e22f09e5SJianlong Huang #endif 309