1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (C) 2021 StarFive Technology Co., Ltd. 4 * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/starfive-jh7100.h> 9#include <dt-bindings/reset/starfive-jh7100.h> 10 11/ { 12 compatible = "starfive,jh7100"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu@0 { 21 compatible = "sifive,u74-mc", "riscv"; 22 reg = <0>; 23 d-cache-block-size = <64>; 24 d-cache-sets = <64>; 25 d-cache-size = <32768>; 26 d-tlb-sets = <1>; 27 d-tlb-size = <32>; 28 device_type = "cpu"; 29 i-cache-block-size = <64>; 30 i-cache-sets = <64>; 31 i-cache-size = <32768>; 32 i-tlb-sets = <1>; 33 i-tlb-size = <32>; 34 mmu-type = "riscv,sv39"; 35 riscv,isa = "rv64imafdc"; 36 tlb-split; 37 38 cpu0_intc: interrupt-controller { 39 compatible = "riscv,cpu-intc"; 40 interrupt-controller; 41 #interrupt-cells = <1>; 42 }; 43 }; 44 45 cpu@1 { 46 compatible = "sifive,u74-mc", "riscv"; 47 reg = <1>; 48 d-cache-block-size = <64>; 49 d-cache-sets = <64>; 50 d-cache-size = <32768>; 51 d-tlb-sets = <1>; 52 d-tlb-size = <32>; 53 device_type = "cpu"; 54 i-cache-block-size = <64>; 55 i-cache-sets = <64>; 56 i-cache-size = <32768>; 57 i-tlb-sets = <1>; 58 i-tlb-size = <32>; 59 mmu-type = "riscv,sv39"; 60 riscv,isa = "rv64imafdc"; 61 tlb-split; 62 63 cpu1_intc: interrupt-controller { 64 compatible = "riscv,cpu-intc"; 65 interrupt-controller; 66 #interrupt-cells = <1>; 67 }; 68 }; 69 }; 70 71 osc_sys: osc_sys { 72 compatible = "fixed-clock"; 73 #clock-cells = <0>; 74 /* This value must be overridden by the board */ 75 clock-frequency = <0>; 76 }; 77 78 osc_aud: osc_aud { 79 compatible = "fixed-clock"; 80 #clock-cells = <0>; 81 /* This value must be overridden by the board */ 82 clock-frequency = <0>; 83 }; 84 85 gmac_rmii_ref: gmac_rmii_ref { 86 compatible = "fixed-clock"; 87 #clock-cells = <0>; 88 /* Should be overridden by the board when needed */ 89 clock-frequency = <0>; 90 }; 91 92 gmac_gr_mii_rxclk: gmac_gr_mii_rxclk { 93 compatible = "fixed-clock"; 94 #clock-cells = <0>; 95 /* Should be overridden by the board when needed */ 96 clock-frequency = <0>; 97 }; 98 99 soc { 100 compatible = "simple-bus"; 101 interrupt-parent = <&plic>; 102 #address-cells = <2>; 103 #size-cells = <2>; 104 ranges; 105 106 clint: clint@2000000 { 107 compatible = "starfive,jh7100-clint", "sifive,clint0"; 108 reg = <0x0 0x2000000 0x0 0x10000>; 109 interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 110 &cpu1_intc 3 &cpu1_intc 7>; 111 }; 112 113 plic: interrupt-controller@c000000 { 114 compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0"; 115 reg = <0x0 0xc000000 0x0 0x4000000>; 116 interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9 117 &cpu1_intc 11 &cpu1_intc 9>; 118 interrupt-controller; 119 #address-cells = <0>; 120 #interrupt-cells = <1>; 121 riscv,ndev = <127>; 122 }; 123 124 clkgen: clock-controller@11800000 { 125 compatible = "starfive,jh7100-clkgen"; 126 reg = <0x0 0x11800000 0x0 0x10000>; 127 clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>; 128 clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk"; 129 #clock-cells = <1>; 130 }; 131 132 rstgen: reset-controller@11840000 { 133 compatible = "starfive,jh7100-reset"; 134 reg = <0x0 0x11840000 0x0 0x10000>; 135 #reset-cells = <1>; 136 }; 137 138 i2c0: i2c@118b0000 { 139 compatible = "snps,designware-i2c"; 140 reg = <0x0 0x118b0000 0x0 0x10000>; 141 clocks = <&clkgen JH7100_CLK_I2C0_CORE>, 142 <&clkgen JH7100_CLK_I2C0_APB>; 143 clock-names = "ref", "pclk"; 144 resets = <&rstgen JH7100_RSTN_I2C0_APB>; 145 interrupts = <96>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 status = "disabled"; 149 }; 150 151 i2c1: i2c@118c0000 { 152 compatible = "snps,designware-i2c"; 153 reg = <0x0 0x118c0000 0x0 0x10000>; 154 clocks = <&clkgen JH7100_CLK_I2C1_CORE>, 155 <&clkgen JH7100_CLK_I2C1_APB>; 156 clock-names = "ref", "pclk"; 157 resets = <&rstgen JH7100_RSTN_I2C1_APB>; 158 interrupts = <97>; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 status = "disabled"; 162 }; 163 164 gpio: pinctrl@11910000 { 165 compatible = "starfive,jh7100-pinctrl"; 166 reg = <0x0 0x11910000 0x0 0x10000>, 167 <0x0 0x11858000 0x0 0x1000>; 168 reg-names = "gpio", "padctl"; 169 clocks = <&clkgen JH7100_CLK_GPIO_APB>; 170 resets = <&rstgen JH7100_RSTN_GPIO_APB>; 171 interrupts = <32>; 172 gpio-controller; 173 #gpio-cells = <2>; 174 interrupt-controller; 175 #interrupt-cells = <2>; 176 }; 177 178 uart2: serial@12430000 { 179 compatible = "starfive,jh7100-uart", "snps,dw-apb-uart"; 180 reg = <0x0 0x12430000 0x0 0x10000>; 181 clocks = <&clkgen JH7100_CLK_UART2_CORE>, 182 <&clkgen JH7100_CLK_UART2_APB>; 183 clock-names = "baudclk", "apb_pclk"; 184 resets = <&rstgen JH7100_RSTN_UART2_APB>; 185 interrupts = <72>; 186 reg-io-width = <4>; 187 reg-shift = <2>; 188 status = "disabled"; 189 }; 190 191 uart3: serial@12440000 { 192 compatible = "starfive,jh7100-uart", "snps,dw-apb-uart"; 193 reg = <0x0 0x12440000 0x0 0x10000>; 194 clocks = <&clkgen JH7100_CLK_UART3_CORE>, 195 <&clkgen JH7100_CLK_UART3_APB>; 196 clock-names = "baudclk", "apb_pclk"; 197 resets = <&rstgen JH7100_RSTN_UART3_APB>; 198 interrupts = <73>; 199 reg-io-width = <4>; 200 reg-shift = <2>; 201 status = "disabled"; 202 }; 203 204 i2c2: i2c@12450000 { 205 compatible = "snps,designware-i2c"; 206 reg = <0x0 0x12450000 0x0 0x10000>; 207 clocks = <&clkgen JH7100_CLK_I2C2_CORE>, 208 <&clkgen JH7100_CLK_I2C2_APB>; 209 clock-names = "ref", "pclk"; 210 resets = <&rstgen JH7100_RSTN_I2C2_APB>; 211 interrupts = <74>; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 status = "disabled"; 215 }; 216 217 i2c3: i2c@12460000 { 218 compatible = "snps,designware-i2c"; 219 reg = <0x0 0x12460000 0x0 0x10000>; 220 clocks = <&clkgen JH7100_CLK_I2C3_CORE>, 221 <&clkgen JH7100_CLK_I2C3_APB>; 222 clock-names = "ref", "pclk"; 223 resets = <&rstgen JH7100_RSTN_I2C3_APB>; 224 interrupts = <75>; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 status = "disabled"; 228 }; 229 }; 230}; 231