1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2018-2019 SiFive, Inc */
3
4#include "fu540-c000.dtsi"
5
6/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
7#define RTCCLK_FREQ		1000000
8
9/ {
10	#address-cells = <2>;
11	#size-cells = <2>;
12	model = "SiFive HiFive Unleashed A00";
13	compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
14
15	chosen {
16	};
17
18	cpus {
19		timebase-frequency = <RTCCLK_FREQ>;
20	};
21
22	memory@80000000 {
23		device_type = "memory";
24		reg = <0x0 0x80000000 0x2 0x00000000>;
25	};
26
27	soc {
28	};
29
30	hfclk: hfclk {
31		#clock-cells = <0>;
32		compatible = "fixed-clock";
33		clock-frequency = <33333333>;
34		clock-output-names = "hfclk";
35	};
36
37	rtcclk: rtcclk {
38		#clock-cells = <0>;
39		compatible = "fixed-clock";
40		clock-frequency = <RTCCLK_FREQ>;
41		clock-output-names = "rtcclk";
42	};
43};
44
45&qspi0 {
46	flash@0 {
47		compatible = "issi,is25wp256", "jedec,spi-nor";
48		reg = <0>;
49		spi-max-frequency = <50000000>;
50		m25p,fast-read;
51		spi-tx-bus-width = <4>;
52		spi-rx-bus-width = <4>;
53	};
54};
55
56&qspi2 {
57	status = "okay";
58	mmc@0 {
59		compatible = "mmc-spi-slot";
60		reg = <0>;
61		spi-max-frequency = <20000000>;
62		voltage-ranges = <3300 3300>;
63		disable-wp;
64	};
65};
66