1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2018-2019 SiFive, Inc */
3
4#include "fu540-c000.dtsi"
5
6/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
7#define RTCCLK_FREQ		1000000
8
9/ {
10	#address-cells = <2>;
11	#size-cells = <2>;
12	model = "SiFive HiFive Unleashed A00";
13	compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
14
15	chosen {
16		stdout-path = "serial0";
17	};
18
19	cpus {
20		timebase-frequency = <RTCCLK_FREQ>;
21	};
22
23	memory@80000000 {
24		device_type = "memory";
25		reg = <0x0 0x80000000 0x2 0x00000000>;
26	};
27
28	soc {
29	};
30
31	hfclk: hfclk {
32		#clock-cells = <0>;
33		compatible = "fixed-clock";
34		clock-frequency = <33333333>;
35		clock-output-names = "hfclk";
36	};
37
38	rtcclk: rtcclk {
39		#clock-cells = <0>;
40		compatible = "fixed-clock";
41		clock-frequency = <RTCCLK_FREQ>;
42		clock-output-names = "rtcclk";
43	};
44};
45
46&uart0 {
47	status = "okay";
48};
49
50&uart1 {
51	status = "okay";
52};
53
54&i2c0 {
55	status = "okay";
56};
57
58&qspi0 {
59	status = "okay";
60	flash@0 {
61		compatible = "issi,is25wp256", "jedec,spi-nor";
62		reg = <0>;
63		spi-max-frequency = <50000000>;
64		m25p,fast-read;
65		spi-tx-bus-width = <4>;
66		spi-rx-bus-width = <4>;
67	};
68};
69
70&qspi2 {
71	status = "okay";
72	mmc@0 {
73		compatible = "mmc-spi-slot";
74		reg = <0>;
75		spi-max-frequency = <20000000>;
76		voltage-ranges = <3300 3300>;
77		disable-wp;
78	};
79};
80
81&eth0 {
82	status = "okay";
83	phy-mode = "gmii";
84	phy-handle = <&phy0>;
85	phy0: ethernet-phy@0 {
86		reg = <0>;
87	};
88};
89
90&pwm0 {
91	status = "okay";
92};
93
94&pwm1 {
95	status = "okay";
96};
97