1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2018-2019 SiFive, Inc */
3
4/dts-v1/;
5
6#include <dt-bindings/clock/sifive-fu540-prci.h>
7
8/ {
9	#address-cells = <2>;
10	#size-cells = <2>;
11	compatible = "sifive,fu540-c000", "sifive,fu540";
12
13	aliases {
14		serial0 = &uart0;
15		serial1 = &uart1;
16		ethernet0 = &eth0;
17	};
18
19	chosen {
20	};
21
22	cpus {
23		#address-cells = <1>;
24		#size-cells = <0>;
25		cpu0: cpu@0 {
26			compatible = "sifive,e51", "sifive,rocket0", "riscv";
27			device_type = "cpu";
28			i-cache-block-size = <64>;
29			i-cache-sets = <128>;
30			i-cache-size = <16384>;
31			reg = <0>;
32			riscv,isa = "rv64imac";
33			status = "disabled";
34			cpu0_intc: interrupt-controller {
35				#interrupt-cells = <1>;
36				compatible = "riscv,cpu-intc";
37				interrupt-controller;
38			};
39		};
40		cpu1: cpu@1 {
41			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
42			d-cache-block-size = <64>;
43			d-cache-sets = <64>;
44			d-cache-size = <32768>;
45			d-tlb-sets = <1>;
46			d-tlb-size = <32>;
47			device_type = "cpu";
48			i-cache-block-size = <64>;
49			i-cache-sets = <64>;
50			i-cache-size = <32768>;
51			i-tlb-sets = <1>;
52			i-tlb-size = <32>;
53			mmu-type = "riscv,sv39";
54			reg = <1>;
55			riscv,isa = "rv64imafdc";
56			tlb-split;
57			next-level-cache = <&l2cache>;
58			cpu1_intc: interrupt-controller {
59				#interrupt-cells = <1>;
60				compatible = "riscv,cpu-intc";
61				interrupt-controller;
62			};
63		};
64		cpu2: cpu@2 {
65			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
66			d-cache-block-size = <64>;
67			d-cache-sets = <64>;
68			d-cache-size = <32768>;
69			d-tlb-sets = <1>;
70			d-tlb-size = <32>;
71			device_type = "cpu";
72			i-cache-block-size = <64>;
73			i-cache-sets = <64>;
74			i-cache-size = <32768>;
75			i-tlb-sets = <1>;
76			i-tlb-size = <32>;
77			mmu-type = "riscv,sv39";
78			reg = <2>;
79			riscv,isa = "rv64imafdc";
80			tlb-split;
81			next-level-cache = <&l2cache>;
82			cpu2_intc: interrupt-controller {
83				#interrupt-cells = <1>;
84				compatible = "riscv,cpu-intc";
85				interrupt-controller;
86			};
87		};
88		cpu3: cpu@3 {
89			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
90			d-cache-block-size = <64>;
91			d-cache-sets = <64>;
92			d-cache-size = <32768>;
93			d-tlb-sets = <1>;
94			d-tlb-size = <32>;
95			device_type = "cpu";
96			i-cache-block-size = <64>;
97			i-cache-sets = <64>;
98			i-cache-size = <32768>;
99			i-tlb-sets = <1>;
100			i-tlb-size = <32>;
101			mmu-type = "riscv,sv39";
102			reg = <3>;
103			riscv,isa = "rv64imafdc";
104			tlb-split;
105			next-level-cache = <&l2cache>;
106			cpu3_intc: interrupt-controller {
107				#interrupt-cells = <1>;
108				compatible = "riscv,cpu-intc";
109				interrupt-controller;
110			};
111		};
112		cpu4: cpu@4 {
113			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
114			d-cache-block-size = <64>;
115			d-cache-sets = <64>;
116			d-cache-size = <32768>;
117			d-tlb-sets = <1>;
118			d-tlb-size = <32>;
119			device_type = "cpu";
120			i-cache-block-size = <64>;
121			i-cache-sets = <64>;
122			i-cache-size = <32768>;
123			i-tlb-sets = <1>;
124			i-tlb-size = <32>;
125			mmu-type = "riscv,sv39";
126			reg = <4>;
127			riscv,isa = "rv64imafdc";
128			tlb-split;
129			next-level-cache = <&l2cache>;
130			cpu4_intc: interrupt-controller {
131				#interrupt-cells = <1>;
132				compatible = "riscv,cpu-intc";
133				interrupt-controller;
134			};
135		};
136	};
137	soc {
138		#address-cells = <2>;
139		#size-cells = <2>;
140		compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
141		ranges;
142		plic0: interrupt-controller@c000000 {
143			#interrupt-cells = <1>;
144			compatible = "sifive,plic-1.0.0";
145			reg = <0x0 0xc000000 0x0 0x4000000>;
146			riscv,ndev = <53>;
147			interrupt-controller;
148			interrupts-extended = <
149				&cpu0_intc 0xffffffff
150				&cpu1_intc 0xffffffff &cpu1_intc 9
151				&cpu2_intc 0xffffffff &cpu2_intc 9
152				&cpu3_intc 0xffffffff &cpu3_intc 9
153				&cpu4_intc 0xffffffff &cpu4_intc 9>;
154		};
155		prci: clock-controller@10000000 {
156			compatible = "sifive,fu540-c000-prci";
157			reg = <0x0 0x10000000 0x0 0x1000>;
158			clocks = <&hfclk>, <&rtcclk>;
159			#clock-cells = <1>;
160		};
161		uart0: serial@10010000 {
162			compatible = "sifive,fu540-c000-uart", "sifive,uart0";
163			reg = <0x0 0x10010000 0x0 0x1000>;
164			interrupt-parent = <&plic0>;
165			interrupts = <4>;
166			clocks = <&prci PRCI_CLK_TLCLK>;
167			status = "disabled";
168		};
169		dma: dma@3000000 {
170			compatible = "sifive,fu540-c000-pdma";
171			reg = <0x0 0x3000000 0x0 0x8000>;
172			interrupt-parent = <&plic0>;
173			interrupts = <23 24 25 26 27 28 29 30>;
174			#dma-cells = <1>;
175		};
176		uart1: serial@10011000 {
177			compatible = "sifive,fu540-c000-uart", "sifive,uart0";
178			reg = <0x0 0x10011000 0x0 0x1000>;
179			interrupt-parent = <&plic0>;
180			interrupts = <5>;
181			clocks = <&prci PRCI_CLK_TLCLK>;
182			status = "disabled";
183		};
184		i2c0: i2c@10030000 {
185			compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
186			reg = <0x0 0x10030000 0x0 0x1000>;
187			interrupt-parent = <&plic0>;
188			interrupts = <50>;
189			clocks = <&prci PRCI_CLK_TLCLK>;
190			reg-shift = <2>;
191			reg-io-width = <1>;
192			#address-cells = <1>;
193			#size-cells = <0>;
194			status = "disabled";
195		};
196		qspi0: spi@10040000 {
197			compatible = "sifive,fu540-c000-spi", "sifive,spi0";
198			reg = <0x0 0x10040000 0x0 0x1000
199			       0x0 0x20000000 0x0 0x10000000>;
200			interrupt-parent = <&plic0>;
201			interrupts = <51>;
202			clocks = <&prci PRCI_CLK_TLCLK>;
203			#address-cells = <1>;
204			#size-cells = <0>;
205			status = "disabled";
206		};
207		qspi1: spi@10041000 {
208			compatible = "sifive,fu540-c000-spi", "sifive,spi0";
209			reg = <0x0 0x10041000 0x0 0x1000
210			       0x0 0x30000000 0x0 0x10000000>;
211			interrupt-parent = <&plic0>;
212			interrupts = <52>;
213			clocks = <&prci PRCI_CLK_TLCLK>;
214			#address-cells = <1>;
215			#size-cells = <0>;
216			status = "disabled";
217		};
218		qspi2: spi@10050000 {
219			compatible = "sifive,fu540-c000-spi", "sifive,spi0";
220			reg = <0x0 0x10050000 0x0 0x1000>;
221			interrupt-parent = <&plic0>;
222			interrupts = <6>;
223			clocks = <&prci PRCI_CLK_TLCLK>;
224			#address-cells = <1>;
225			#size-cells = <0>;
226			status = "disabled";
227		};
228		eth0: ethernet@10090000 {
229			compatible = "sifive,fu540-c000-gem";
230			interrupt-parent = <&plic0>;
231			interrupts = <53>;
232			reg = <0x0 0x10090000 0x0 0x2000
233			       0x0 0x100a0000 0x0 0x1000>;
234			local-mac-address = [00 00 00 00 00 00];
235			clock-names = "pclk", "hclk";
236			clocks = <&prci PRCI_CLK_GEMGXLPLL>,
237				 <&prci PRCI_CLK_GEMGXLPLL>;
238			#address-cells = <1>;
239			#size-cells = <0>;
240			status = "disabled";
241		};
242		pwm0: pwm@10020000 {
243			compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
244			reg = <0x0 0x10020000 0x0 0x1000>;
245			interrupt-parent = <&plic0>;
246			interrupts = <42 43 44 45>;
247			clocks = <&prci PRCI_CLK_TLCLK>;
248			#pwm-cells = <3>;
249			status = "disabled";
250		};
251		pwm1: pwm@10021000 {
252			compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
253			reg = <0x0 0x10021000 0x0 0x1000>;
254			interrupt-parent = <&plic0>;
255			interrupts = <46 47 48 49>;
256			clocks = <&prci PRCI_CLK_TLCLK>;
257			#pwm-cells = <3>;
258			status = "disabled";
259		};
260		l2cache: cache-controller@2010000 {
261			compatible = "sifive,fu540-c000-ccache", "cache";
262			cache-block-size = <64>;
263			cache-level = <2>;
264			cache-sets = <1024>;
265			cache-size = <2097152>;
266			cache-unified;
267			interrupt-parent = <&plic0>;
268			interrupts = <1 2 3>;
269			reg = <0x0 0x2010000 0x0 0x1000>;
270		};
271		gpio: gpio@10060000 {
272			compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
273			interrupt-parent = <&plic0>;
274			interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>,
275				     <14>, <15>, <16>, <17>, <18>, <19>, <20>,
276				     <21>, <22>;
277			reg = <0x0 0x10060000 0x0 0x1000>;
278			gpio-controller;
279			#gpio-cells = <2>;
280			interrupt-controller;
281			#interrupt-cells = <2>;
282			clocks = <&prci PRCI_CLK_TLCLK>;
283			status = "disabled";
284		};
285	};
286};
287