1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2018-2019 SiFive, Inc */ 3 4/dts-v1/; 5 6#include <dt-bindings/clock/sifive-fu540-prci.h> 7 8/ { 9 #address-cells = <2>; 10 #size-cells = <2>; 11 compatible = "sifive,fu540-c000", "sifive,fu540"; 12 13 aliases { 14 serial0 = &uart0; 15 serial1 = &uart1; 16 }; 17 18 chosen { 19 }; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 cpu0: cpu@0 { 25 compatible = "sifive,e51", "sifive,rocket0", "riscv"; 26 device_type = "cpu"; 27 i-cache-block-size = <64>; 28 i-cache-sets = <128>; 29 i-cache-size = <16384>; 30 reg = <0>; 31 riscv,isa = "rv64imac"; 32 status = "disabled"; 33 cpu0_intc: interrupt-controller { 34 #interrupt-cells = <1>; 35 compatible = "riscv,cpu-intc"; 36 interrupt-controller; 37 }; 38 }; 39 cpu1: cpu@1 { 40 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 41 d-cache-block-size = <64>; 42 d-cache-sets = <64>; 43 d-cache-size = <32768>; 44 d-tlb-sets = <1>; 45 d-tlb-size = <32>; 46 device_type = "cpu"; 47 i-cache-block-size = <64>; 48 i-cache-sets = <64>; 49 i-cache-size = <32768>; 50 i-tlb-sets = <1>; 51 i-tlb-size = <32>; 52 mmu-type = "riscv,sv39"; 53 reg = <1>; 54 riscv,isa = "rv64imafdc"; 55 tlb-split; 56 cpu1_intc: interrupt-controller { 57 #interrupt-cells = <1>; 58 compatible = "riscv,cpu-intc"; 59 interrupt-controller; 60 }; 61 }; 62 cpu2: cpu@2 { 63 clock-frequency = <0>; 64 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 65 d-cache-block-size = <64>; 66 d-cache-sets = <64>; 67 d-cache-size = <32768>; 68 d-tlb-sets = <1>; 69 d-tlb-size = <32>; 70 device_type = "cpu"; 71 i-cache-block-size = <64>; 72 i-cache-sets = <64>; 73 i-cache-size = <32768>; 74 i-tlb-sets = <1>; 75 i-tlb-size = <32>; 76 mmu-type = "riscv,sv39"; 77 reg = <2>; 78 riscv,isa = "rv64imafdc"; 79 tlb-split; 80 cpu2_intc: interrupt-controller { 81 #interrupt-cells = <1>; 82 compatible = "riscv,cpu-intc"; 83 interrupt-controller; 84 }; 85 }; 86 cpu3: cpu@3 { 87 clock-frequency = <0>; 88 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 89 d-cache-block-size = <64>; 90 d-cache-sets = <64>; 91 d-cache-size = <32768>; 92 d-tlb-sets = <1>; 93 d-tlb-size = <32>; 94 device_type = "cpu"; 95 i-cache-block-size = <64>; 96 i-cache-sets = <64>; 97 i-cache-size = <32768>; 98 i-tlb-sets = <1>; 99 i-tlb-size = <32>; 100 mmu-type = "riscv,sv39"; 101 reg = <3>; 102 riscv,isa = "rv64imafdc"; 103 tlb-split; 104 cpu3_intc: interrupt-controller { 105 #interrupt-cells = <1>; 106 compatible = "riscv,cpu-intc"; 107 interrupt-controller; 108 }; 109 }; 110 cpu4: cpu@4 { 111 clock-frequency = <0>; 112 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 113 d-cache-block-size = <64>; 114 d-cache-sets = <64>; 115 d-cache-size = <32768>; 116 d-tlb-sets = <1>; 117 d-tlb-size = <32>; 118 device_type = "cpu"; 119 i-cache-block-size = <64>; 120 i-cache-sets = <64>; 121 i-cache-size = <32768>; 122 i-tlb-sets = <1>; 123 i-tlb-size = <32>; 124 mmu-type = "riscv,sv39"; 125 reg = <4>; 126 riscv,isa = "rv64imafdc"; 127 tlb-split; 128 cpu4_intc: interrupt-controller { 129 #interrupt-cells = <1>; 130 compatible = "riscv,cpu-intc"; 131 interrupt-controller; 132 }; 133 }; 134 }; 135 soc { 136 #address-cells = <2>; 137 #size-cells = <2>; 138 compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; 139 ranges; 140 plic0: interrupt-controller@c000000 { 141 #interrupt-cells = <1>; 142 compatible = "sifive,plic-1.0.0"; 143 reg = <0x0 0xc000000 0x0 0x4000000>; 144 riscv,ndev = <53>; 145 interrupt-controller; 146 interrupts-extended = < 147 &cpu0_intc 0xffffffff 148 &cpu1_intc 0xffffffff &cpu1_intc 9 149 &cpu2_intc 0xffffffff &cpu2_intc 9 150 &cpu3_intc 0xffffffff &cpu3_intc 9 151 &cpu4_intc 0xffffffff &cpu4_intc 9>; 152 }; 153 prci: clock-controller@10000000 { 154 compatible = "sifive,fu540-c000-prci"; 155 reg = <0x0 0x10000000 0x0 0x1000>; 156 clocks = <&hfclk>, <&rtcclk>; 157 #clock-cells = <1>; 158 }; 159 uart0: serial@10010000 { 160 compatible = "sifive,fu540-c000-uart", "sifive,uart0"; 161 reg = <0x0 0x10010000 0x0 0x1000>; 162 interrupt-parent = <&plic0>; 163 interrupts = <4>; 164 clocks = <&prci PRCI_CLK_TLCLK>; 165 status = "disabled"; 166 }; 167 uart1: serial@10011000 { 168 compatible = "sifive,fu540-c000-uart", "sifive,uart0"; 169 reg = <0x0 0x10011000 0x0 0x1000>; 170 interrupt-parent = <&plic0>; 171 interrupts = <5>; 172 clocks = <&prci PRCI_CLK_TLCLK>; 173 status = "disabled"; 174 }; 175 i2c0: i2c@10030000 { 176 compatible = "sifive,fu540-c000-i2c", "sifive,i2c0"; 177 reg = <0x0 0x10030000 0x0 0x1000>; 178 interrupt-parent = <&plic0>; 179 interrupts = <50>; 180 clocks = <&prci PRCI_CLK_TLCLK>; 181 reg-shift = <2>; 182 reg-io-width = <1>; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 status = "disabled"; 186 }; 187 qspi0: spi@10040000 { 188 compatible = "sifive,fu540-c000-spi", "sifive,spi0"; 189 reg = <0x0 0x10040000 0x0 0x1000 190 0x0 0x20000000 0x0 0x10000000>; 191 interrupt-parent = <&plic0>; 192 interrupts = <51>; 193 clocks = <&prci PRCI_CLK_TLCLK>; 194 #address-cells = <1>; 195 #size-cells = <0>; 196 status = "disabled"; 197 }; 198 qspi1: spi@10041000 { 199 compatible = "sifive,fu540-c000-spi", "sifive,spi0"; 200 reg = <0x0 0x10041000 0x0 0x1000 201 0x0 0x30000000 0x0 0x10000000>; 202 interrupt-parent = <&plic0>; 203 interrupts = <52>; 204 clocks = <&prci PRCI_CLK_TLCLK>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 status = "disabled"; 208 }; 209 qspi2: spi@10050000 { 210 compatible = "sifive,fu540-c000-spi", "sifive,spi0"; 211 reg = <0x0 0x10050000 0x0 0x1000>; 212 interrupt-parent = <&plic0>; 213 interrupts = <6>; 214 clocks = <&prci PRCI_CLK_TLCLK>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 status = "disabled"; 218 }; 219 eth0: ethernet@10090000 { 220 compatible = "sifive,fu540-c000-gem"; 221 interrupt-parent = <&plic0>; 222 interrupts = <53>; 223 reg = <0x0 0x10090000 0x0 0x2000 224 0x0 0x100a0000 0x0 0x1000>; 225 local-mac-address = [00 00 00 00 00 00]; 226 clock-names = "pclk", "hclk"; 227 clocks = <&prci PRCI_CLK_GEMGXLPLL>, 228 <&prci PRCI_CLK_GEMGXLPLL>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 status = "disabled"; 232 }; 233 234 }; 235}; 236