1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/Five SoC 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9 10#define SOC_PERIPHERAL_IRQ(nr) (nr + 32) 11 12#include <arm64/renesas/r9a07g043.dtsi> 13 14/ { 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 timebase-frequency = <12000000>; 19 20 cpu0: cpu@0 { 21 compatible = "andestech,ax45mp", "riscv"; 22 device_type = "cpu"; 23 reg = <0x0>; 24 status = "okay"; 25 riscv,isa = "rv64imafdc"; 26 mmu-type = "riscv,sv39"; 27 i-cache-size = <0x8000>; 28 i-cache-line-size = <0x40>; 29 d-cache-size = <0x8000>; 30 d-cache-line-size = <0x40>; 31 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; 32 33 cpu0_intc: interrupt-controller { 34 #interrupt-cells = <1>; 35 compatible = "riscv,cpu-intc"; 36 interrupt-controller; 37 }; 38 }; 39 }; 40}; 41 42&soc { 43 interrupt-parent = <&plic>; 44 45 plic: interrupt-controller@12c00000 { 46 compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; 47 #interrupt-cells = <2>; 48 #address-cells = <0>; 49 riscv,ndev = <511>; 50 interrupt-controller; 51 reg = <0x0 0x12c00000 0 0x400000>; 52 clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; 53 power-domains = <&cpg>; 54 resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; 55 interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>; 56 }; 57}; 58