1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2020-2021 Microchip Technology Inc */ 3 4/dts-v1/; 5#include "dt-bindings/clock/microchip,mpfs-clock.h" 6 7/ { 8 #address-cells = <2>; 9 #size-cells = <2>; 10 model = "Microchip PolarFire SoC"; 11 compatible = "microchip,mpfs"; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu0: cpu@0 { 18 compatible = "sifive,e51", "sifive,rocket0", "riscv"; 19 device_type = "cpu"; 20 i-cache-block-size = <64>; 21 i-cache-sets = <128>; 22 i-cache-size = <16384>; 23 reg = <0>; 24 riscv,isa = "rv64imac"; 25 clocks = <&clkcfg CLK_CPU>; 26 status = "disabled"; 27 28 cpu0_intc: interrupt-controller { 29 #interrupt-cells = <1>; 30 compatible = "riscv,cpu-intc"; 31 interrupt-controller; 32 }; 33 }; 34 35 cpu1: cpu@1 { 36 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 37 d-cache-block-size = <64>; 38 d-cache-sets = <64>; 39 d-cache-size = <32768>; 40 d-tlb-sets = <1>; 41 d-tlb-size = <32>; 42 device_type = "cpu"; 43 i-cache-block-size = <64>; 44 i-cache-sets = <64>; 45 i-cache-size = <32768>; 46 i-tlb-sets = <1>; 47 i-tlb-size = <32>; 48 mmu-type = "riscv,sv39"; 49 reg = <1>; 50 riscv,isa = "rv64imafdc"; 51 clocks = <&clkcfg CLK_CPU>; 52 tlb-split; 53 next-level-cache = <&cctrllr>; 54 status = "okay"; 55 56 cpu1_intc: interrupt-controller { 57 #interrupt-cells = <1>; 58 compatible = "riscv,cpu-intc"; 59 interrupt-controller; 60 }; 61 }; 62 63 cpu2: cpu@2 { 64 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 65 d-cache-block-size = <64>; 66 d-cache-sets = <64>; 67 d-cache-size = <32768>; 68 d-tlb-sets = <1>; 69 d-tlb-size = <32>; 70 device_type = "cpu"; 71 i-cache-block-size = <64>; 72 i-cache-sets = <64>; 73 i-cache-size = <32768>; 74 i-tlb-sets = <1>; 75 i-tlb-size = <32>; 76 mmu-type = "riscv,sv39"; 77 reg = <2>; 78 riscv,isa = "rv64imafdc"; 79 clocks = <&clkcfg CLK_CPU>; 80 tlb-split; 81 next-level-cache = <&cctrllr>; 82 status = "okay"; 83 84 cpu2_intc: interrupt-controller { 85 #interrupt-cells = <1>; 86 compatible = "riscv,cpu-intc"; 87 interrupt-controller; 88 }; 89 }; 90 91 cpu3: cpu@3 { 92 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 93 d-cache-block-size = <64>; 94 d-cache-sets = <64>; 95 d-cache-size = <32768>; 96 d-tlb-sets = <1>; 97 d-tlb-size = <32>; 98 device_type = "cpu"; 99 i-cache-block-size = <64>; 100 i-cache-sets = <64>; 101 i-cache-size = <32768>; 102 i-tlb-sets = <1>; 103 i-tlb-size = <32>; 104 mmu-type = "riscv,sv39"; 105 reg = <3>; 106 riscv,isa = "rv64imafdc"; 107 clocks = <&clkcfg CLK_CPU>; 108 tlb-split; 109 next-level-cache = <&cctrllr>; 110 status = "okay"; 111 112 cpu3_intc: interrupt-controller { 113 #interrupt-cells = <1>; 114 compatible = "riscv,cpu-intc"; 115 interrupt-controller; 116 }; 117 }; 118 119 cpu4: cpu@4 { 120 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 121 d-cache-block-size = <64>; 122 d-cache-sets = <64>; 123 d-cache-size = <32768>; 124 d-tlb-sets = <1>; 125 d-tlb-size = <32>; 126 device_type = "cpu"; 127 i-cache-block-size = <64>; 128 i-cache-sets = <64>; 129 i-cache-size = <32768>; 130 i-tlb-sets = <1>; 131 i-tlb-size = <32>; 132 mmu-type = "riscv,sv39"; 133 reg = <4>; 134 riscv,isa = "rv64imafdc"; 135 clocks = <&clkcfg CLK_CPU>; 136 tlb-split; 137 next-level-cache = <&cctrllr>; 138 status = "okay"; 139 cpu4_intc: interrupt-controller { 140 #interrupt-cells = <1>; 141 compatible = "riscv,cpu-intc"; 142 interrupt-controller; 143 }; 144 }; 145 }; 146 147 refclk: mssrefclk { 148 compatible = "fixed-clock"; 149 #clock-cells = <0>; 150 }; 151 152 syscontroller: syscontroller { 153 compatible = "microchip,mpfs-sys-controller"; 154 mboxes = <&mbox 0>; 155 }; 156 157 soc { 158 #address-cells = <2>; 159 #size-cells = <2>; 160 compatible = "simple-bus"; 161 ranges; 162 163 cctrllr: cache-controller@2010000 { 164 compatible = "sifive,fu540-c000-ccache", "cache"; 165 reg = <0x0 0x2010000 0x0 0x1000>; 166 cache-block-size = <64>; 167 cache-level = <2>; 168 cache-sets = <1024>; 169 cache-size = <2097152>; 170 cache-unified; 171 interrupt-parent = <&plic>; 172 interrupts = <1>, <2>, <3>; 173 }; 174 175 clint: clint@2000000 { 176 compatible = "sifive,fu540-c000-clint", "sifive,clint0"; 177 reg = <0x0 0x2000000 0x0 0xC000>; 178 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 179 <&cpu1_intc 3>, <&cpu1_intc 7>, 180 <&cpu2_intc 3>, <&cpu2_intc 7>, 181 <&cpu3_intc 3>, <&cpu3_intc 7>, 182 <&cpu4_intc 3>, <&cpu4_intc 7>; 183 }; 184 185 plic: interrupt-controller@c000000 { 186 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; 187 reg = <0x0 0xc000000 0x0 0x4000000>; 188 #address-cells = <0>; 189 #interrupt-cells = <1>; 190 interrupt-controller; 191 interrupts-extended = <&cpu0_intc 11>, 192 <&cpu1_intc 11>, <&cpu1_intc 9>, 193 <&cpu2_intc 11>, <&cpu2_intc 9>, 194 <&cpu3_intc 11>, <&cpu3_intc 9>, 195 <&cpu4_intc 11>, <&cpu4_intc 9>; 196 riscv,ndev = <186>; 197 }; 198 199 pdma: dma-controller@3000000 { 200 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0"; 201 reg = <0x0 0x3000000 0x0 0x8000>; 202 interrupt-parent = <&plic>; 203 interrupts = <5 6>, <7 8>, <9 10>, <11 12>; 204 dma-channels = <4>; 205 #dma-cells = <1>; 206 }; 207 208 clkcfg: clkcfg@20002000 { 209 compatible = "microchip,mpfs-clkcfg"; 210 reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; 211 clocks = <&refclk>; 212 #clock-cells = <1>; 213 }; 214 215 mmuart0: serial@20000000 { 216 compatible = "ns16550a"; 217 reg = <0x0 0x20000000 0x0 0x400>; 218 reg-io-width = <4>; 219 reg-shift = <2>; 220 interrupt-parent = <&plic>; 221 interrupts = <90>; 222 current-speed = <115200>; 223 clocks = <&clkcfg CLK_MMUART0>; 224 status = "disabled"; /* Reserved for the HSS */ 225 }; 226 227 mmuart1: serial@20100000 { 228 compatible = "ns16550a"; 229 reg = <0x0 0x20100000 0x0 0x400>; 230 reg-io-width = <4>; 231 reg-shift = <2>; 232 interrupt-parent = <&plic>; 233 interrupts = <91>; 234 current-speed = <115200>; 235 clocks = <&clkcfg CLK_MMUART1>; 236 status = "disabled"; 237 }; 238 239 mmuart2: serial@20102000 { 240 compatible = "ns16550a"; 241 reg = <0x0 0x20102000 0x0 0x400>; 242 reg-io-width = <4>; 243 reg-shift = <2>; 244 interrupt-parent = <&plic>; 245 interrupts = <92>; 246 current-speed = <115200>; 247 clocks = <&clkcfg CLK_MMUART2>; 248 status = "disabled"; 249 }; 250 251 mmuart3: serial@20104000 { 252 compatible = "ns16550a"; 253 reg = <0x0 0x20104000 0x0 0x400>; 254 reg-io-width = <4>; 255 reg-shift = <2>; 256 interrupt-parent = <&plic>; 257 interrupts = <93>; 258 current-speed = <115200>; 259 clocks = <&clkcfg CLK_MMUART3>; 260 status = "disabled"; 261 }; 262 263 mmuart4: serial@20106000 { 264 compatible = "ns16550a"; 265 reg = <0x0 0x20106000 0x0 0x400>; 266 reg-io-width = <4>; 267 reg-shift = <2>; 268 interrupt-parent = <&plic>; 269 interrupts = <94>; 270 clocks = <&clkcfg CLK_MMUART4>; 271 current-speed = <115200>; 272 status = "disabled"; 273 }; 274 275 /* Common node entry for emmc/sd */ 276 mmc: mmc@20008000 { 277 compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc"; 278 reg = <0x0 0x20008000 0x0 0x1000>; 279 interrupt-parent = <&plic>; 280 interrupts = <88>; 281 clocks = <&clkcfg CLK_MMC>; 282 max-frequency = <200000000>; 283 status = "disabled"; 284 }; 285 286 spi0: spi@20108000 { 287 compatible = "microchip,mpfs-spi"; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 reg = <0x0 0x20108000 0x0 0x1000>; 291 interrupt-parent = <&plic>; 292 interrupts = <54>; 293 clocks = <&clkcfg CLK_SPI0>; 294 spi-max-frequency = <25000000>; 295 status = "disabled"; 296 }; 297 298 spi1: spi@20109000 { 299 compatible = "microchip,mpfs-spi"; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 reg = <0x0 0x20109000 0x0 0x1000>; 303 interrupt-parent = <&plic>; 304 interrupts = <55>; 305 clocks = <&clkcfg CLK_SPI1>; 306 spi-max-frequency = <25000000>; 307 status = "disabled"; 308 }; 309 310 qspi: spi@21000000 { 311 compatible = "microchip,mpfs-qspi"; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 reg = <0x0 0x21000000 0x0 0x1000>; 315 interrupt-parent = <&plic>; 316 interrupts = <85>; 317 clocks = <&clkcfg CLK_QSPI>; 318 spi-max-frequency = <25000000>; 319 status = "disabled"; 320 }; 321 322 i2c0: i2c@2010a000 { 323 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; 324 reg = <0x0 0x2010a000 0x0 0x1000>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 interrupt-parent = <&plic>; 328 interrupts = <58>; 329 clocks = <&clkcfg CLK_I2C0>; 330 clock-frequency = <100000>; 331 status = "disabled"; 332 }; 333 334 i2c1: i2c@2010b000 { 335 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; 336 reg = <0x0 0x2010b000 0x0 0x1000>; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 interrupt-parent = <&plic>; 340 interrupts = <61>; 341 clocks = <&clkcfg CLK_I2C1>; 342 clock-frequency = <100000>; 343 status = "disabled"; 344 }; 345 346 mac0: ethernet@20110000 { 347 compatible = "cdns,macb"; 348 reg = <0x0 0x20110000 0x0 0x2000>; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 interrupt-parent = <&plic>; 352 interrupts = <64>, <65>, <66>, <67>, <68>, <69>; 353 local-mac-address = [00 00 00 00 00 00]; 354 clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; 355 clock-names = "pclk", "hclk"; 356 status = "disabled"; 357 }; 358 359 mac1: ethernet@20112000 { 360 compatible = "cdns,macb"; 361 reg = <0x0 0x20112000 0x0 0x2000>; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 interrupt-parent = <&plic>; 365 interrupts = <70>, <71>, <72>, <73>, <74>, <75>; 366 local-mac-address = [00 00 00 00 00 00]; 367 clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; 368 clock-names = "pclk", "hclk"; 369 status = "disabled"; 370 }; 371 372 gpio0: gpio@20120000 { 373 compatible = "microchip,mpfs-gpio"; 374 reg = <0x0 0x20120000 0x0 0x1000>; 375 interrupt-parent = <&plic>; 376 interrupt-controller; 377 #interrupt-cells = <1>; 378 clocks = <&clkcfg CLK_GPIO0>; 379 gpio-controller; 380 #gpio-cells = <2>; 381 status = "disabled"; 382 }; 383 384 gpio1: gpio@20121000 { 385 compatible = "microchip,mpfs-gpio"; 386 reg = <0x0 0x20121000 0x0 0x1000>; 387 interrupt-parent = <&plic>; 388 interrupt-controller; 389 #interrupt-cells = <1>; 390 clocks = <&clkcfg CLK_GPIO1>; 391 gpio-controller; 392 #gpio-cells = <2>; 393 status = "disabled"; 394 }; 395 396 gpio2: gpio@20122000 { 397 compatible = "microchip,mpfs-gpio"; 398 reg = <0x0 0x20122000 0x0 0x1000>; 399 interrupt-parent = <&plic>; 400 interrupt-controller; 401 #interrupt-cells = <1>; 402 clocks = <&clkcfg CLK_GPIO2>; 403 gpio-controller; 404 #gpio-cells = <2>; 405 status = "disabled"; 406 }; 407 408 rtc: rtc@20124000 { 409 compatible = "microchip,mpfs-rtc"; 410 reg = <0x0 0x20124000 0x0 0x1000>; 411 interrupt-parent = <&plic>; 412 interrupts = <80>, <81>; 413 clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; 414 clock-names = "rtc", "rtcref"; 415 status = "disabled"; 416 }; 417 418 usb: usb@20201000 { 419 compatible = "microchip,mpfs-musb"; 420 reg = <0x0 0x20201000 0x0 0x1000>; 421 interrupt-parent = <&plic>; 422 interrupts = <86>, <87>; 423 clocks = <&clkcfg CLK_USB>; 424 interrupt-names = "dma","mc"; 425 status = "disabled"; 426 }; 427 428 pcie: pcie@2000000000 { 429 compatible = "microchip,pcie-host-1.0"; 430 #address-cells = <0x3>; 431 #interrupt-cells = <0x1>; 432 #size-cells = <0x2>; 433 device_type = "pci"; 434 reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; 435 reg-names = "cfg", "apb"; 436 bus-range = <0x0 0x7f>; 437 interrupt-parent = <&plic>; 438 interrupts = <119>; 439 interrupt-map = <0 0 0 1 &pcie_intc 0>, 440 <0 0 0 2 &pcie_intc 1>, 441 <0 0 0 3 &pcie_intc 2>, 442 <0 0 0 4 &pcie_intc 3>; 443 interrupt-map-mask = <0 0 0 7>; 444 clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; 445 clock-names = "fic0", "fic1", "fic3"; 446 ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; 447 msi-parent = <&pcie>; 448 msi-controller; 449 microchip,axi-m-atr0 = <0x10 0x0>; 450 status = "disabled"; 451 pcie_intc: legacy-interrupt-controller { 452 #address-cells = <0>; 453 #interrupt-cells = <1>; 454 interrupt-controller; 455 }; 456 }; 457 458 mbox: mailbox@37020000 { 459 compatible = "microchip,mpfs-mailbox"; 460 reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; 461 interrupt-parent = <&plic>; 462 interrupts = <96>; 463 #mbox-cells = <1>; 464 status = "disabled"; 465 }; 466 }; 467}; 468