1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2020-2021 Microchip Technology Inc */ 3 4/dts-v1/; 5#include "dt-bindings/clock/microchip,mpfs-clock.h" 6 7/ { 8 #address-cells = <2>; 9 #size-cells = <2>; 10 model = "Microchip PolarFire SoC"; 11 compatible = "microchip,mpfs"; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu0: cpu@0 { 18 compatible = "sifive,e51", "sifive,rocket0", "riscv"; 19 device_type = "cpu"; 20 i-cache-block-size = <64>; 21 i-cache-sets = <128>; 22 i-cache-size = <16384>; 23 reg = <0>; 24 riscv,isa = "rv64imac"; 25 clocks = <&clkcfg CLK_CPU>; 26 status = "disabled"; 27 28 cpu0_intc: interrupt-controller { 29 #interrupt-cells = <1>; 30 compatible = "riscv,cpu-intc"; 31 interrupt-controller; 32 }; 33 }; 34 35 cpu1: cpu@1 { 36 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 37 d-cache-block-size = <64>; 38 d-cache-sets = <64>; 39 d-cache-size = <32768>; 40 d-tlb-sets = <1>; 41 d-tlb-size = <32>; 42 device_type = "cpu"; 43 i-cache-block-size = <64>; 44 i-cache-sets = <64>; 45 i-cache-size = <32768>; 46 i-tlb-sets = <1>; 47 i-tlb-size = <32>; 48 mmu-type = "riscv,sv39"; 49 reg = <1>; 50 riscv,isa = "rv64imafdc"; 51 clocks = <&clkcfg CLK_CPU>; 52 tlb-split; 53 status = "okay"; 54 55 cpu1_intc: interrupt-controller { 56 #interrupt-cells = <1>; 57 compatible = "riscv,cpu-intc"; 58 interrupt-controller; 59 }; 60 }; 61 62 cpu2: cpu@2 { 63 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 64 d-cache-block-size = <64>; 65 d-cache-sets = <64>; 66 d-cache-size = <32768>; 67 d-tlb-sets = <1>; 68 d-tlb-size = <32>; 69 device_type = "cpu"; 70 i-cache-block-size = <64>; 71 i-cache-sets = <64>; 72 i-cache-size = <32768>; 73 i-tlb-sets = <1>; 74 i-tlb-size = <32>; 75 mmu-type = "riscv,sv39"; 76 reg = <2>; 77 riscv,isa = "rv64imafdc"; 78 clocks = <&clkcfg CLK_CPU>; 79 tlb-split; 80 status = "okay"; 81 82 cpu2_intc: interrupt-controller { 83 #interrupt-cells = <1>; 84 compatible = "riscv,cpu-intc"; 85 interrupt-controller; 86 }; 87 }; 88 89 cpu3: cpu@3 { 90 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 91 d-cache-block-size = <64>; 92 d-cache-sets = <64>; 93 d-cache-size = <32768>; 94 d-tlb-sets = <1>; 95 d-tlb-size = <32>; 96 device_type = "cpu"; 97 i-cache-block-size = <64>; 98 i-cache-sets = <64>; 99 i-cache-size = <32768>; 100 i-tlb-sets = <1>; 101 i-tlb-size = <32>; 102 mmu-type = "riscv,sv39"; 103 reg = <3>; 104 riscv,isa = "rv64imafdc"; 105 clocks = <&clkcfg CLK_CPU>; 106 tlb-split; 107 status = "okay"; 108 109 cpu3_intc: interrupt-controller { 110 #interrupt-cells = <1>; 111 compatible = "riscv,cpu-intc"; 112 interrupt-controller; 113 }; 114 }; 115 116 cpu4: cpu@4 { 117 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 118 d-cache-block-size = <64>; 119 d-cache-sets = <64>; 120 d-cache-size = <32768>; 121 d-tlb-sets = <1>; 122 d-tlb-size = <32>; 123 device_type = "cpu"; 124 i-cache-block-size = <64>; 125 i-cache-sets = <64>; 126 i-cache-size = <32768>; 127 i-tlb-sets = <1>; 128 i-tlb-size = <32>; 129 mmu-type = "riscv,sv39"; 130 reg = <4>; 131 riscv,isa = "rv64imafdc"; 132 clocks = <&clkcfg CLK_CPU>; 133 tlb-split; 134 status = "okay"; 135 cpu4_intc: interrupt-controller { 136 #interrupt-cells = <1>; 137 compatible = "riscv,cpu-intc"; 138 interrupt-controller; 139 }; 140 }; 141 }; 142 143 refclk: mssrefclk { 144 compatible = "fixed-clock"; 145 #clock-cells = <0>; 146 }; 147 148 syscontroller: syscontroller { 149 compatible = "microchip,mpfs-sys-controller"; 150 mboxes = <&mbox 0>; 151 }; 152 153 soc { 154 #address-cells = <2>; 155 #size-cells = <2>; 156 compatible = "simple-bus"; 157 ranges; 158 159 cctrllr: cache-controller@2010000 { 160 compatible = "sifive,fu540-c000-ccache", "cache"; 161 reg = <0x0 0x2010000 0x0 0x1000>; 162 cache-block-size = <64>; 163 cache-level = <2>; 164 cache-sets = <1024>; 165 cache-size = <2097152>; 166 cache-unified; 167 interrupt-parent = <&plic>; 168 interrupts = <1>, <2>, <3>; 169 }; 170 171 clint: clint@2000000 { 172 compatible = "sifive,fu540-c000-clint", "sifive,clint0"; 173 reg = <0x0 0x2000000 0x0 0xC000>; 174 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 175 <&cpu1_intc 3>, <&cpu1_intc 7>, 176 <&cpu2_intc 3>, <&cpu2_intc 7>, 177 <&cpu3_intc 3>, <&cpu3_intc 7>, 178 <&cpu4_intc 3>, <&cpu4_intc 7>; 179 }; 180 181 plic: interrupt-controller@c000000 { 182 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; 183 reg = <0x0 0xc000000 0x0 0x4000000>; 184 #address-cells = <0>; 185 #interrupt-cells = <1>; 186 interrupt-controller; 187 interrupts-extended = <&cpu0_intc 11>, 188 <&cpu1_intc 11>, <&cpu1_intc 9>, 189 <&cpu2_intc 11>, <&cpu2_intc 9>, 190 <&cpu3_intc 11>, <&cpu3_intc 9>, 191 <&cpu4_intc 11>, <&cpu4_intc 9>; 192 riscv,ndev = <186>; 193 }; 194 195 pdma: dma-controller@3000000 { 196 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0"; 197 reg = <0x0 0x3000000 0x0 0x8000>; 198 interrupt-parent = <&plic>; 199 interrupts = <5 6>, <7 8>, <9 10>, <11 12>; 200 dma-channels = <4>; 201 #dma-cells = <1>; 202 }; 203 204 clkcfg: clkcfg@20002000 { 205 compatible = "microchip,mpfs-clkcfg"; 206 reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; 207 clocks = <&refclk>; 208 #clock-cells = <1>; 209 }; 210 211 mmuart0: serial@20000000 { 212 compatible = "ns16550a"; 213 reg = <0x0 0x20000000 0x0 0x400>; 214 reg-io-width = <4>; 215 reg-shift = <2>; 216 interrupt-parent = <&plic>; 217 interrupts = <90>; 218 current-speed = <115200>; 219 clocks = <&clkcfg CLK_MMUART0>; 220 status = "disabled"; /* Reserved for the HSS */ 221 }; 222 223 mmuart1: serial@20100000 { 224 compatible = "ns16550a"; 225 reg = <0x0 0x20100000 0x0 0x400>; 226 reg-io-width = <4>; 227 reg-shift = <2>; 228 interrupt-parent = <&plic>; 229 interrupts = <91>; 230 current-speed = <115200>; 231 clocks = <&clkcfg CLK_MMUART1>; 232 status = "disabled"; 233 }; 234 235 mmuart2: serial@20102000 { 236 compatible = "ns16550a"; 237 reg = <0x0 0x20102000 0x0 0x400>; 238 reg-io-width = <4>; 239 reg-shift = <2>; 240 interrupt-parent = <&plic>; 241 interrupts = <92>; 242 current-speed = <115200>; 243 clocks = <&clkcfg CLK_MMUART2>; 244 status = "disabled"; 245 }; 246 247 mmuart3: serial@20104000 { 248 compatible = "ns16550a"; 249 reg = <0x0 0x20104000 0x0 0x400>; 250 reg-io-width = <4>; 251 reg-shift = <2>; 252 interrupt-parent = <&plic>; 253 interrupts = <93>; 254 current-speed = <115200>; 255 clocks = <&clkcfg CLK_MMUART3>; 256 status = "disabled"; 257 }; 258 259 mmuart4: serial@20106000 { 260 compatible = "ns16550a"; 261 reg = <0x0 0x20106000 0x0 0x400>; 262 reg-io-width = <4>; 263 reg-shift = <2>; 264 interrupt-parent = <&plic>; 265 interrupts = <94>; 266 clocks = <&clkcfg CLK_MMUART4>; 267 current-speed = <115200>; 268 status = "disabled"; 269 }; 270 271 /* Common node entry for emmc/sd */ 272 mmc: mmc@20008000 { 273 compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc"; 274 reg = <0x0 0x20008000 0x0 0x1000>; 275 interrupt-parent = <&plic>; 276 interrupts = <88>; 277 clocks = <&clkcfg CLK_MMC>; 278 max-frequency = <200000000>; 279 status = "disabled"; 280 }; 281 282 spi0: spi@20108000 { 283 compatible = "microchip,mpfs-spi"; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 reg = <0x0 0x20108000 0x0 0x1000>; 287 interrupt-parent = <&plic>; 288 interrupts = <54>; 289 clocks = <&clkcfg CLK_SPI0>; 290 spi-max-frequency = <25000000>; 291 status = "disabled"; 292 }; 293 294 spi1: spi@20109000 { 295 compatible = "microchip,mpfs-spi"; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 reg = <0x0 0x20109000 0x0 0x1000>; 299 interrupt-parent = <&plic>; 300 interrupts = <55>; 301 clocks = <&clkcfg CLK_SPI1>; 302 spi-max-frequency = <25000000>; 303 status = "disabled"; 304 }; 305 306 qspi: spi@21000000 { 307 compatible = "microchip,mpfs-qspi"; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 reg = <0x0 0x21000000 0x0 0x1000>; 311 interrupt-parent = <&plic>; 312 interrupts = <85>; 313 clocks = <&clkcfg CLK_QSPI>; 314 spi-max-frequency = <25000000>; 315 status = "disabled"; 316 }; 317 318 i2c0: i2c@2010a000 { 319 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; 320 reg = <0x0 0x2010a000 0x0 0x1000>; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 interrupt-parent = <&plic>; 324 interrupts = <58>; 325 clocks = <&clkcfg CLK_I2C0>; 326 clock-frequency = <100000>; 327 status = "disabled"; 328 }; 329 330 i2c1: i2c@2010b000 { 331 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; 332 reg = <0x0 0x2010b000 0x0 0x1000>; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 interrupt-parent = <&plic>; 336 interrupts = <61>; 337 clocks = <&clkcfg CLK_I2C1>; 338 clock-frequency = <100000>; 339 status = "disabled"; 340 }; 341 342 mac0: ethernet@20110000 { 343 compatible = "cdns,macb"; 344 reg = <0x0 0x20110000 0x0 0x2000>; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 interrupt-parent = <&plic>; 348 interrupts = <64>, <65>, <66>, <67>, <68>, <69>; 349 local-mac-address = [00 00 00 00 00 00]; 350 clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; 351 clock-names = "pclk", "hclk"; 352 status = "disabled"; 353 }; 354 355 mac1: ethernet@20112000 { 356 compatible = "cdns,macb"; 357 reg = <0x0 0x20112000 0x0 0x2000>; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 interrupt-parent = <&plic>; 361 interrupts = <70>, <71>, <72>, <73>, <74>, <75>; 362 local-mac-address = [00 00 00 00 00 00]; 363 clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; 364 clock-names = "pclk", "hclk"; 365 status = "disabled"; 366 }; 367 368 gpio0: gpio@20120000 { 369 compatible = "microchip,mpfs-gpio"; 370 reg = <0x0 0x20120000 0x0 0x1000>; 371 interrupt-parent = <&plic>; 372 interrupt-controller; 373 #interrupt-cells = <1>; 374 clocks = <&clkcfg CLK_GPIO0>; 375 gpio-controller; 376 #gpio-cells = <2>; 377 status = "disabled"; 378 }; 379 380 gpio1: gpio@20121000 { 381 compatible = "microchip,mpfs-gpio"; 382 reg = <0x0 0x20121000 0x0 0x1000>; 383 interrupt-parent = <&plic>; 384 interrupt-controller; 385 #interrupt-cells = <1>; 386 clocks = <&clkcfg CLK_GPIO1>; 387 gpio-controller; 388 #gpio-cells = <2>; 389 status = "disabled"; 390 }; 391 392 gpio2: gpio@20122000 { 393 compatible = "microchip,mpfs-gpio"; 394 reg = <0x0 0x20122000 0x0 0x1000>; 395 interrupt-parent = <&plic>; 396 interrupt-controller; 397 #interrupt-cells = <1>; 398 clocks = <&clkcfg CLK_GPIO2>; 399 gpio-controller; 400 #gpio-cells = <2>; 401 status = "disabled"; 402 }; 403 404 rtc: rtc@20124000 { 405 compatible = "microchip,mpfs-rtc"; 406 reg = <0x0 0x20124000 0x0 0x1000>; 407 interrupt-parent = <&plic>; 408 interrupts = <80>, <81>; 409 clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; 410 clock-names = "rtc", "rtcref"; 411 status = "disabled"; 412 }; 413 414 usb: usb@20201000 { 415 compatible = "microchip,mpfs-musb"; 416 reg = <0x0 0x20201000 0x0 0x1000>; 417 interrupt-parent = <&plic>; 418 interrupts = <86>, <87>; 419 clocks = <&clkcfg CLK_USB>; 420 interrupt-names = "dma","mc"; 421 status = "disabled"; 422 }; 423 424 pcie: pcie@2000000000 { 425 compatible = "microchip,pcie-host-1.0"; 426 #address-cells = <0x3>; 427 #interrupt-cells = <0x1>; 428 #size-cells = <0x2>; 429 device_type = "pci"; 430 reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; 431 reg-names = "cfg", "apb"; 432 bus-range = <0x0 0x7f>; 433 interrupt-parent = <&plic>; 434 interrupts = <119>; 435 interrupt-map = <0 0 0 1 &pcie_intc 0>, 436 <0 0 0 2 &pcie_intc 1>, 437 <0 0 0 3 &pcie_intc 2>, 438 <0 0 0 4 &pcie_intc 3>; 439 interrupt-map-mask = <0 0 0 7>; 440 clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; 441 clock-names = "fic0", "fic1", "fic3"; 442 ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; 443 msi-parent = <&pcie>; 444 msi-controller; 445 microchip,axi-m-atr0 = <0x10 0x0>; 446 status = "disabled"; 447 pcie_intc: legacy-interrupt-controller { 448 #address-cells = <0>; 449 #interrupt-cells = <1>; 450 interrupt-controller; 451 }; 452 }; 453 454 mbox: mailbox@37020000 { 455 compatible = "microchip,mpfs-mailbox"; 456 reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; 457 interrupt-parent = <&plic>; 458 interrupts = <96>; 459 #mbox-cells = <1>; 460 status = "disabled"; 461 }; 462 }; 463}; 464