1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2020-2021 Microchip Technology Inc */ 3 4/dts-v1/; 5#include "dt-bindings/clock/microchip,mpfs-clock.h" 6 7/ { 8 #address-cells = <2>; 9 #size-cells = <2>; 10 model = "Microchip PolarFire SoC"; 11 compatible = "microchip,mpfs"; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu0: cpu@0 { 18 compatible = "sifive,e51", "sifive,rocket0", "riscv"; 19 device_type = "cpu"; 20 i-cache-block-size = <64>; 21 i-cache-sets = <128>; 22 i-cache-size = <16384>; 23 reg = <0>; 24 riscv,isa = "rv64imac"; 25 clocks = <&clkcfg CLK_CPU>; 26 status = "disabled"; 27 28 cpu0_intc: interrupt-controller { 29 #interrupt-cells = <1>; 30 compatible = "riscv,cpu-intc"; 31 interrupt-controller; 32 }; 33 }; 34 35 cpu1: cpu@1 { 36 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 37 d-cache-block-size = <64>; 38 d-cache-sets = <64>; 39 d-cache-size = <32768>; 40 d-tlb-sets = <1>; 41 d-tlb-size = <32>; 42 device_type = "cpu"; 43 i-cache-block-size = <64>; 44 i-cache-sets = <64>; 45 i-cache-size = <32768>; 46 i-tlb-sets = <1>; 47 i-tlb-size = <32>; 48 mmu-type = "riscv,sv39"; 49 reg = <1>; 50 riscv,isa = "rv64imafdc"; 51 clocks = <&clkcfg CLK_CPU>; 52 tlb-split; 53 status = "okay"; 54 55 cpu1_intc: interrupt-controller { 56 #interrupt-cells = <1>; 57 compatible = "riscv,cpu-intc"; 58 interrupt-controller; 59 }; 60 }; 61 62 cpu2: cpu@2 { 63 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 64 d-cache-block-size = <64>; 65 d-cache-sets = <64>; 66 d-cache-size = <32768>; 67 d-tlb-sets = <1>; 68 d-tlb-size = <32>; 69 device_type = "cpu"; 70 i-cache-block-size = <64>; 71 i-cache-sets = <64>; 72 i-cache-size = <32768>; 73 i-tlb-sets = <1>; 74 i-tlb-size = <32>; 75 mmu-type = "riscv,sv39"; 76 reg = <2>; 77 riscv,isa = "rv64imafdc"; 78 clocks = <&clkcfg CLK_CPU>; 79 tlb-split; 80 status = "okay"; 81 82 cpu2_intc: interrupt-controller { 83 #interrupt-cells = <1>; 84 compatible = "riscv,cpu-intc"; 85 interrupt-controller; 86 }; 87 }; 88 89 cpu3: cpu@3 { 90 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 91 d-cache-block-size = <64>; 92 d-cache-sets = <64>; 93 d-cache-size = <32768>; 94 d-tlb-sets = <1>; 95 d-tlb-size = <32>; 96 device_type = "cpu"; 97 i-cache-block-size = <64>; 98 i-cache-sets = <64>; 99 i-cache-size = <32768>; 100 i-tlb-sets = <1>; 101 i-tlb-size = <32>; 102 mmu-type = "riscv,sv39"; 103 reg = <3>; 104 riscv,isa = "rv64imafdc"; 105 clocks = <&clkcfg CLK_CPU>; 106 tlb-split; 107 status = "okay"; 108 109 cpu3_intc: interrupt-controller { 110 #interrupt-cells = <1>; 111 compatible = "riscv,cpu-intc"; 112 interrupt-controller; 113 }; 114 }; 115 116 cpu4: cpu@4 { 117 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 118 d-cache-block-size = <64>; 119 d-cache-sets = <64>; 120 d-cache-size = <32768>; 121 d-tlb-sets = <1>; 122 d-tlb-size = <32>; 123 device_type = "cpu"; 124 i-cache-block-size = <64>; 125 i-cache-sets = <64>; 126 i-cache-size = <32768>; 127 i-tlb-sets = <1>; 128 i-tlb-size = <32>; 129 mmu-type = "riscv,sv39"; 130 reg = <4>; 131 riscv,isa = "rv64imafdc"; 132 clocks = <&clkcfg CLK_CPU>; 133 tlb-split; 134 status = "okay"; 135 cpu4_intc: interrupt-controller { 136 #interrupt-cells = <1>; 137 compatible = "riscv,cpu-intc"; 138 interrupt-controller; 139 }; 140 }; 141 }; 142 143 refclk: mssrefclk { 144 compatible = "fixed-clock"; 145 #clock-cells = <0>; 146 }; 147 148 syscontroller: syscontroller { 149 compatible = "microchip,mpfs-sys-controller"; 150 mboxes = <&mbox 0>; 151 }; 152 153 soc { 154 #address-cells = <2>; 155 #size-cells = <2>; 156 compatible = "simple-bus"; 157 ranges; 158 159 cctrllr: cache-controller@2010000 { 160 compatible = "sifive,fu540-c000-ccache", "cache"; 161 reg = <0x0 0x2010000 0x0 0x1000>; 162 cache-block-size = <64>; 163 cache-level = <2>; 164 cache-sets = <1024>; 165 cache-size = <2097152>; 166 cache-unified; 167 interrupt-parent = <&plic>; 168 interrupts = <1>, <2>, <3>; 169 }; 170 171 clint: clint@2000000 { 172 compatible = "sifive,fu540-c000-clint", "sifive,clint0"; 173 reg = <0x0 0x2000000 0x0 0xC000>; 174 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 175 <&cpu1_intc 3>, <&cpu1_intc 7>, 176 <&cpu2_intc 3>, <&cpu2_intc 7>, 177 <&cpu3_intc 3>, <&cpu3_intc 7>, 178 <&cpu4_intc 3>, <&cpu4_intc 7>; 179 }; 180 181 plic: interrupt-controller@c000000 { 182 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; 183 reg = <0x0 0xc000000 0x0 0x4000000>; 184 #address-cells = <0>; 185 #interrupt-cells = <1>; 186 interrupt-controller; 187 interrupts-extended = <&cpu0_intc 11>, 188 <&cpu1_intc 11>, <&cpu1_intc 9>, 189 <&cpu2_intc 11>, <&cpu2_intc 9>, 190 <&cpu3_intc 11>, <&cpu3_intc 9>, 191 <&cpu4_intc 11>, <&cpu4_intc 9>; 192 riscv,ndev = <186>; 193 }; 194 195 clkcfg: clkcfg@20002000 { 196 compatible = "microchip,mpfs-clkcfg"; 197 reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; 198 clocks = <&refclk>; 199 #clock-cells = <1>; 200 }; 201 202 mmuart0: serial@20000000 { 203 compatible = "ns16550a"; 204 reg = <0x0 0x20000000 0x0 0x400>; 205 reg-io-width = <4>; 206 reg-shift = <2>; 207 interrupt-parent = <&plic>; 208 interrupts = <90>; 209 current-speed = <115200>; 210 clocks = <&clkcfg CLK_MMUART0>; 211 status = "disabled"; /* Reserved for the HSS */ 212 }; 213 214 mmuart1: serial@20100000 { 215 compatible = "ns16550a"; 216 reg = <0x0 0x20100000 0x0 0x400>; 217 reg-io-width = <4>; 218 reg-shift = <2>; 219 interrupt-parent = <&plic>; 220 interrupts = <91>; 221 current-speed = <115200>; 222 clocks = <&clkcfg CLK_MMUART1>; 223 status = "disabled"; 224 }; 225 226 mmuart2: serial@20102000 { 227 compatible = "ns16550a"; 228 reg = <0x0 0x20102000 0x0 0x400>; 229 reg-io-width = <4>; 230 reg-shift = <2>; 231 interrupt-parent = <&plic>; 232 interrupts = <92>; 233 current-speed = <115200>; 234 clocks = <&clkcfg CLK_MMUART2>; 235 status = "disabled"; 236 }; 237 238 mmuart3: serial@20104000 { 239 compatible = "ns16550a"; 240 reg = <0x0 0x20104000 0x0 0x400>; 241 reg-io-width = <4>; 242 reg-shift = <2>; 243 interrupt-parent = <&plic>; 244 interrupts = <93>; 245 current-speed = <115200>; 246 clocks = <&clkcfg CLK_MMUART3>; 247 status = "disabled"; 248 }; 249 250 mmuart4: serial@20106000 { 251 compatible = "ns16550a"; 252 reg = <0x0 0x20106000 0x0 0x400>; 253 reg-io-width = <4>; 254 reg-shift = <2>; 255 interrupt-parent = <&plic>; 256 interrupts = <94>; 257 clocks = <&clkcfg CLK_MMUART4>; 258 current-speed = <115200>; 259 status = "disabled"; 260 }; 261 262 /* Common node entry for emmc/sd */ 263 mmc: mmc@20008000 { 264 compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc"; 265 reg = <0x0 0x20008000 0x0 0x1000>; 266 interrupt-parent = <&plic>; 267 interrupts = <88>; 268 clocks = <&clkcfg CLK_MMC>; 269 max-frequency = <200000000>; 270 status = "disabled"; 271 }; 272 273 spi0: spi@20108000 { 274 compatible = "microchip,mpfs-spi"; 275 #address-cells = <1>; 276 #size-cells = <0>; 277 reg = <0x0 0x20108000 0x0 0x1000>; 278 interrupt-parent = <&plic>; 279 interrupts = <54>; 280 clocks = <&clkcfg CLK_SPI0>; 281 spi-max-frequency = <25000000>; 282 status = "disabled"; 283 }; 284 285 spi1: spi@20109000 { 286 compatible = "microchip,mpfs-spi"; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 reg = <0x0 0x20109000 0x0 0x1000>; 290 interrupt-parent = <&plic>; 291 interrupts = <55>; 292 clocks = <&clkcfg CLK_SPI1>; 293 spi-max-frequency = <25000000>; 294 status = "disabled"; 295 }; 296 297 qspi: spi@21000000 { 298 compatible = "microchip,mpfs-qspi"; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 reg = <0x0 0x21000000 0x0 0x1000>; 302 interrupt-parent = <&plic>; 303 interrupts = <85>; 304 clocks = <&clkcfg CLK_QSPI>; 305 spi-max-frequency = <25000000>; 306 status = "disabled"; 307 }; 308 309 i2c0: i2c@2010a000 { 310 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; 311 reg = <0x0 0x2010a000 0x0 0x1000>; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 interrupt-parent = <&plic>; 315 interrupts = <58>; 316 clocks = <&clkcfg CLK_I2C0>; 317 clock-frequency = <100000>; 318 status = "disabled"; 319 }; 320 321 i2c1: i2c@2010b000 { 322 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; 323 reg = <0x0 0x2010b000 0x0 0x1000>; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 interrupt-parent = <&plic>; 327 interrupts = <61>; 328 clocks = <&clkcfg CLK_I2C1>; 329 clock-frequency = <100000>; 330 status = "disabled"; 331 }; 332 333 mac0: ethernet@20110000 { 334 compatible = "cdns,macb"; 335 reg = <0x0 0x20110000 0x0 0x2000>; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 interrupt-parent = <&plic>; 339 interrupts = <64>, <65>, <66>, <67>, <68>, <69>; 340 local-mac-address = [00 00 00 00 00 00]; 341 clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; 342 clock-names = "pclk", "hclk"; 343 status = "disabled"; 344 }; 345 346 mac1: ethernet@20112000 { 347 compatible = "cdns,macb"; 348 reg = <0x0 0x20112000 0x0 0x2000>; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 interrupt-parent = <&plic>; 352 interrupts = <70>, <71>, <72>, <73>, <74>, <75>; 353 local-mac-address = [00 00 00 00 00 00]; 354 clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; 355 clock-names = "pclk", "hclk"; 356 status = "disabled"; 357 }; 358 359 gpio0: gpio@20120000 { 360 compatible = "microchip,mpfs-gpio"; 361 reg = <0x0 0x20120000 0x0 0x1000>; 362 interrupt-parent = <&plic>; 363 interrupt-controller; 364 #interrupt-cells = <1>; 365 clocks = <&clkcfg CLK_GPIO0>; 366 gpio-controller; 367 #gpio-cells = <2>; 368 status = "disabled"; 369 }; 370 371 gpio1: gpio@20121000 { 372 compatible = "microchip,mpfs-gpio"; 373 reg = <0x0 0x20121000 0x0 0x1000>; 374 interrupt-parent = <&plic>; 375 interrupt-controller; 376 #interrupt-cells = <1>; 377 clocks = <&clkcfg CLK_GPIO1>; 378 gpio-controller; 379 #gpio-cells = <2>; 380 status = "disabled"; 381 }; 382 383 gpio2: gpio@20122000 { 384 compatible = "microchip,mpfs-gpio"; 385 reg = <0x0 0x20122000 0x0 0x1000>; 386 interrupt-parent = <&plic>; 387 interrupt-controller; 388 #interrupt-cells = <1>; 389 clocks = <&clkcfg CLK_GPIO2>; 390 gpio-controller; 391 #gpio-cells = <2>; 392 status = "disabled"; 393 }; 394 395 rtc: rtc@20124000 { 396 compatible = "microchip,mpfs-rtc"; 397 reg = <0x0 0x20124000 0x0 0x1000>; 398 interrupt-parent = <&plic>; 399 interrupts = <80>, <81>; 400 clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; 401 clock-names = "rtc", "rtcref"; 402 status = "disabled"; 403 }; 404 405 usb: usb@20201000 { 406 compatible = "microchip,mpfs-musb"; 407 reg = <0x0 0x20201000 0x0 0x1000>; 408 interrupt-parent = <&plic>; 409 interrupts = <86>, <87>; 410 clocks = <&clkcfg CLK_USB>; 411 interrupt-names = "dma","mc"; 412 status = "disabled"; 413 }; 414 415 pcie: pcie@2000000000 { 416 compatible = "microchip,pcie-host-1.0"; 417 #address-cells = <0x3>; 418 #interrupt-cells = <0x1>; 419 #size-cells = <0x2>; 420 device_type = "pci"; 421 reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; 422 reg-names = "cfg", "apb"; 423 bus-range = <0x0 0x7f>; 424 interrupt-parent = <&plic>; 425 interrupts = <119>; 426 interrupt-map = <0 0 0 1 &pcie_intc 0>, 427 <0 0 0 2 &pcie_intc 1>, 428 <0 0 0 3 &pcie_intc 2>, 429 <0 0 0 4 &pcie_intc 3>; 430 interrupt-map-mask = <0 0 0 7>; 431 clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; 432 clock-names = "fic0", "fic1", "fic3"; 433 ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; 434 msi-parent = <&pcie>; 435 msi-controller; 436 microchip,axi-m-atr0 = <0x10 0x0>; 437 status = "disabled"; 438 pcie_intc: legacy-interrupt-controller { 439 #address-cells = <0>; 440 #interrupt-cells = <1>; 441 interrupt-controller; 442 }; 443 }; 444 445 mbox: mailbox@37020000 { 446 compatible = "microchip,mpfs-mailbox"; 447 reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; 448 interrupt-parent = <&plic>; 449 interrupts = <96>; 450 #mbox-cells = <1>; 451 status = "disabled"; 452 }; 453 }; 454}; 455