1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2020-2021 Microchip Technology Inc */ 3 4/dts-v1/; 5#include "dt-bindings/clock/microchip,mpfs-clock.h" 6 7/ { 8 #address-cells = <2>; 9 #size-cells = <2>; 10 model = "Microchip PolarFire SoC"; 11 compatible = "microchip,mpfs"; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu0: cpu@0 { 18 compatible = "sifive,e51", "sifive,rocket0", "riscv"; 19 device_type = "cpu"; 20 i-cache-block-size = <64>; 21 i-cache-sets = <128>; 22 i-cache-size = <16384>; 23 reg = <0>; 24 riscv,isa = "rv64imac"; 25 clocks = <&clkcfg CLK_CPU>; 26 status = "disabled"; 27 28 cpu0_intc: interrupt-controller { 29 #interrupt-cells = <1>; 30 compatible = "riscv,cpu-intc"; 31 interrupt-controller; 32 }; 33 }; 34 35 cpu1: cpu@1 { 36 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 37 d-cache-block-size = <64>; 38 d-cache-sets = <64>; 39 d-cache-size = <32768>; 40 d-tlb-sets = <1>; 41 d-tlb-size = <32>; 42 device_type = "cpu"; 43 i-cache-block-size = <64>; 44 i-cache-sets = <64>; 45 i-cache-size = <32768>; 46 i-tlb-sets = <1>; 47 i-tlb-size = <32>; 48 mmu-type = "riscv,sv39"; 49 reg = <1>; 50 riscv,isa = "rv64imafdc"; 51 clocks = <&clkcfg CLK_CPU>; 52 tlb-split; 53 next-level-cache = <&cctrllr>; 54 status = "okay"; 55 56 cpu1_intc: interrupt-controller { 57 #interrupt-cells = <1>; 58 compatible = "riscv,cpu-intc"; 59 interrupt-controller; 60 }; 61 }; 62 63 cpu2: cpu@2 { 64 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 65 d-cache-block-size = <64>; 66 d-cache-sets = <64>; 67 d-cache-size = <32768>; 68 d-tlb-sets = <1>; 69 d-tlb-size = <32>; 70 device_type = "cpu"; 71 i-cache-block-size = <64>; 72 i-cache-sets = <64>; 73 i-cache-size = <32768>; 74 i-tlb-sets = <1>; 75 i-tlb-size = <32>; 76 mmu-type = "riscv,sv39"; 77 reg = <2>; 78 riscv,isa = "rv64imafdc"; 79 clocks = <&clkcfg CLK_CPU>; 80 tlb-split; 81 next-level-cache = <&cctrllr>; 82 status = "okay"; 83 84 cpu2_intc: interrupt-controller { 85 #interrupt-cells = <1>; 86 compatible = "riscv,cpu-intc"; 87 interrupt-controller; 88 }; 89 }; 90 91 cpu3: cpu@3 { 92 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 93 d-cache-block-size = <64>; 94 d-cache-sets = <64>; 95 d-cache-size = <32768>; 96 d-tlb-sets = <1>; 97 d-tlb-size = <32>; 98 device_type = "cpu"; 99 i-cache-block-size = <64>; 100 i-cache-sets = <64>; 101 i-cache-size = <32768>; 102 i-tlb-sets = <1>; 103 i-tlb-size = <32>; 104 mmu-type = "riscv,sv39"; 105 reg = <3>; 106 riscv,isa = "rv64imafdc"; 107 clocks = <&clkcfg CLK_CPU>; 108 tlb-split; 109 next-level-cache = <&cctrllr>; 110 status = "okay"; 111 112 cpu3_intc: interrupt-controller { 113 #interrupt-cells = <1>; 114 compatible = "riscv,cpu-intc"; 115 interrupt-controller; 116 }; 117 }; 118 119 cpu4: cpu@4 { 120 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 121 d-cache-block-size = <64>; 122 d-cache-sets = <64>; 123 d-cache-size = <32768>; 124 d-tlb-sets = <1>; 125 d-tlb-size = <32>; 126 device_type = "cpu"; 127 i-cache-block-size = <64>; 128 i-cache-sets = <64>; 129 i-cache-size = <32768>; 130 i-tlb-sets = <1>; 131 i-tlb-size = <32>; 132 mmu-type = "riscv,sv39"; 133 reg = <4>; 134 riscv,isa = "rv64imafdc"; 135 clocks = <&clkcfg CLK_CPU>; 136 tlb-split; 137 next-level-cache = <&cctrllr>; 138 status = "okay"; 139 cpu4_intc: interrupt-controller { 140 #interrupt-cells = <1>; 141 compatible = "riscv,cpu-intc"; 142 interrupt-controller; 143 }; 144 }; 145 146 cpu-map { 147 cluster0 { 148 core0 { 149 cpu = <&cpu0>; 150 }; 151 152 core1 { 153 cpu = <&cpu1>; 154 }; 155 156 core2 { 157 cpu = <&cpu2>; 158 }; 159 160 core3 { 161 cpu = <&cpu3>; 162 }; 163 164 core4 { 165 cpu = <&cpu4>; 166 }; 167 }; 168 }; 169 }; 170 171 refclk: mssrefclk { 172 compatible = "fixed-clock"; 173 #clock-cells = <0>; 174 }; 175 176 syscontroller: syscontroller { 177 compatible = "microchip,mpfs-sys-controller"; 178 mboxes = <&mbox 0>; 179 }; 180 181 soc { 182 #address-cells = <2>; 183 #size-cells = <2>; 184 compatible = "simple-bus"; 185 ranges; 186 187 cctrllr: cache-controller@2010000 { 188 compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache"; 189 reg = <0x0 0x2010000 0x0 0x1000>; 190 cache-block-size = <64>; 191 cache-level = <2>; 192 cache-sets = <1024>; 193 cache-size = <2097152>; 194 cache-unified; 195 interrupt-parent = <&plic>; 196 interrupts = <1>, <3>, <4>, <2>; 197 }; 198 199 clint: clint@2000000 { 200 compatible = "sifive,fu540-c000-clint", "sifive,clint0"; 201 reg = <0x0 0x2000000 0x0 0xC000>; 202 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 203 <&cpu1_intc 3>, <&cpu1_intc 7>, 204 <&cpu2_intc 3>, <&cpu2_intc 7>, 205 <&cpu3_intc 3>, <&cpu3_intc 7>, 206 <&cpu4_intc 3>, <&cpu4_intc 7>; 207 }; 208 209 plic: interrupt-controller@c000000 { 210 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; 211 reg = <0x0 0xc000000 0x0 0x4000000>; 212 #address-cells = <0>; 213 #interrupt-cells = <1>; 214 interrupt-controller; 215 interrupts-extended = <&cpu0_intc 11>, 216 <&cpu1_intc 11>, <&cpu1_intc 9>, 217 <&cpu2_intc 11>, <&cpu2_intc 9>, 218 <&cpu3_intc 11>, <&cpu3_intc 9>, 219 <&cpu4_intc 11>, <&cpu4_intc 9>; 220 riscv,ndev = <186>; 221 }; 222 223 pdma: dma-controller@3000000 { 224 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0"; 225 reg = <0x0 0x3000000 0x0 0x8000>; 226 interrupt-parent = <&plic>; 227 interrupts = <5 6>, <7 8>, <9 10>, <11 12>; 228 dma-channels = <4>; 229 #dma-cells = <1>; 230 }; 231 232 clkcfg: clkcfg@20002000 { 233 compatible = "microchip,mpfs-clkcfg"; 234 reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; 235 clocks = <&refclk>; 236 #clock-cells = <1>; 237 }; 238 239 ccc_se: clock-controller@38010000 { 240 compatible = "microchip,mpfs-ccc"; 241 reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, 242 <0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>; 243 #clock-cells = <1>; 244 status = "disabled"; 245 }; 246 247 ccc_ne: clock-controller@38040000 { 248 compatible = "microchip,mpfs-ccc"; 249 reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>, 250 <0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>; 251 #clock-cells = <1>; 252 status = "disabled"; 253 }; 254 255 ccc_nw: clock-controller@38100000 { 256 compatible = "microchip,mpfs-ccc"; 257 reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>, 258 <0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>; 259 #clock-cells = <1>; 260 status = "disabled"; 261 }; 262 263 ccc_sw: clock-controller@38400000 { 264 compatible = "microchip,mpfs-ccc"; 265 reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>, 266 <0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>; 267 #clock-cells = <1>; 268 status = "disabled"; 269 }; 270 271 mmuart0: serial@20000000 { 272 compatible = "ns16550a"; 273 reg = <0x0 0x20000000 0x0 0x400>; 274 reg-io-width = <4>; 275 reg-shift = <2>; 276 interrupt-parent = <&plic>; 277 interrupts = <90>; 278 current-speed = <115200>; 279 clocks = <&clkcfg CLK_MMUART0>; 280 status = "disabled"; /* Reserved for the HSS */ 281 }; 282 283 mmuart1: serial@20100000 { 284 compatible = "ns16550a"; 285 reg = <0x0 0x20100000 0x0 0x400>; 286 reg-io-width = <4>; 287 reg-shift = <2>; 288 interrupt-parent = <&plic>; 289 interrupts = <91>; 290 current-speed = <115200>; 291 clocks = <&clkcfg CLK_MMUART1>; 292 status = "disabled"; 293 }; 294 295 mmuart2: serial@20102000 { 296 compatible = "ns16550a"; 297 reg = <0x0 0x20102000 0x0 0x400>; 298 reg-io-width = <4>; 299 reg-shift = <2>; 300 interrupt-parent = <&plic>; 301 interrupts = <92>; 302 current-speed = <115200>; 303 clocks = <&clkcfg CLK_MMUART2>; 304 status = "disabled"; 305 }; 306 307 mmuart3: serial@20104000 { 308 compatible = "ns16550a"; 309 reg = <0x0 0x20104000 0x0 0x400>; 310 reg-io-width = <4>; 311 reg-shift = <2>; 312 interrupt-parent = <&plic>; 313 interrupts = <93>; 314 current-speed = <115200>; 315 clocks = <&clkcfg CLK_MMUART3>; 316 status = "disabled"; 317 }; 318 319 mmuart4: serial@20106000 { 320 compatible = "ns16550a"; 321 reg = <0x0 0x20106000 0x0 0x400>; 322 reg-io-width = <4>; 323 reg-shift = <2>; 324 interrupt-parent = <&plic>; 325 interrupts = <94>; 326 clocks = <&clkcfg CLK_MMUART4>; 327 current-speed = <115200>; 328 status = "disabled"; 329 }; 330 331 /* Common node entry for emmc/sd */ 332 mmc: mmc@20008000 { 333 compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc"; 334 reg = <0x0 0x20008000 0x0 0x1000>; 335 interrupt-parent = <&plic>; 336 interrupts = <88>; 337 clocks = <&clkcfg CLK_MMC>; 338 max-frequency = <200000000>; 339 status = "disabled"; 340 }; 341 342 spi0: spi@20108000 { 343 compatible = "microchip,mpfs-spi"; 344 #address-cells = <1>; 345 #size-cells = <0>; 346 reg = <0x0 0x20108000 0x0 0x1000>; 347 interrupt-parent = <&plic>; 348 interrupts = <54>; 349 clocks = <&clkcfg CLK_SPI0>; 350 status = "disabled"; 351 }; 352 353 spi1: spi@20109000 { 354 compatible = "microchip,mpfs-spi"; 355 #address-cells = <1>; 356 #size-cells = <0>; 357 reg = <0x0 0x20109000 0x0 0x1000>; 358 interrupt-parent = <&plic>; 359 interrupts = <55>; 360 clocks = <&clkcfg CLK_SPI1>; 361 status = "disabled"; 362 }; 363 364 qspi: spi@21000000 { 365 compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2"; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 reg = <0x0 0x21000000 0x0 0x1000>; 369 interrupt-parent = <&plic>; 370 interrupts = <85>; 371 clocks = <&clkcfg CLK_QSPI>; 372 status = "disabled"; 373 }; 374 375 i2c0: i2c@2010a000 { 376 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; 377 reg = <0x0 0x2010a000 0x0 0x1000>; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 interrupt-parent = <&plic>; 381 interrupts = <58>; 382 clocks = <&clkcfg CLK_I2C0>; 383 clock-frequency = <100000>; 384 status = "disabled"; 385 }; 386 387 i2c1: i2c@2010b000 { 388 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; 389 reg = <0x0 0x2010b000 0x0 0x1000>; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 interrupt-parent = <&plic>; 393 interrupts = <61>; 394 clocks = <&clkcfg CLK_I2C1>; 395 clock-frequency = <100000>; 396 status = "disabled"; 397 }; 398 399 can0: can@2010c000 { 400 compatible = "microchip,mpfs-can"; 401 reg = <0x0 0x2010c000 0x0 0x1000>; 402 clocks = <&clkcfg CLK_CAN0>; 403 interrupt-parent = <&plic>; 404 interrupts = <56>; 405 status = "disabled"; 406 }; 407 408 can1: can@2010d000 { 409 compatible = "microchip,mpfs-can"; 410 reg = <0x0 0x2010d000 0x0 0x1000>; 411 clocks = <&clkcfg CLK_CAN1>; 412 interrupt-parent = <&plic>; 413 interrupts = <57>; 414 status = "disabled"; 415 }; 416 417 mac0: ethernet@20110000 { 418 compatible = "cdns,macb"; 419 reg = <0x0 0x20110000 0x0 0x2000>; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 interrupt-parent = <&plic>; 423 interrupts = <64>, <65>, <66>, <67>, <68>, <69>; 424 local-mac-address = [00 00 00 00 00 00]; 425 clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; 426 clock-names = "pclk", "hclk"; 427 status = "disabled"; 428 }; 429 430 mac1: ethernet@20112000 { 431 compatible = "cdns,macb"; 432 reg = <0x0 0x20112000 0x0 0x2000>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 interrupt-parent = <&plic>; 436 interrupts = <70>, <71>, <72>, <73>, <74>, <75>; 437 local-mac-address = [00 00 00 00 00 00]; 438 clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; 439 clock-names = "pclk", "hclk"; 440 status = "disabled"; 441 }; 442 443 gpio0: gpio@20120000 { 444 compatible = "microchip,mpfs-gpio"; 445 reg = <0x0 0x20120000 0x0 0x1000>; 446 interrupt-parent = <&plic>; 447 interrupt-controller; 448 #interrupt-cells = <1>; 449 clocks = <&clkcfg CLK_GPIO0>; 450 gpio-controller; 451 #gpio-cells = <2>; 452 status = "disabled"; 453 }; 454 455 gpio1: gpio@20121000 { 456 compatible = "microchip,mpfs-gpio"; 457 reg = <0x0 0x20121000 0x0 0x1000>; 458 interrupt-parent = <&plic>; 459 interrupt-controller; 460 #interrupt-cells = <1>; 461 clocks = <&clkcfg CLK_GPIO1>; 462 gpio-controller; 463 #gpio-cells = <2>; 464 status = "disabled"; 465 }; 466 467 gpio2: gpio@20122000 { 468 compatible = "microchip,mpfs-gpio"; 469 reg = <0x0 0x20122000 0x0 0x1000>; 470 interrupt-parent = <&plic>; 471 interrupt-controller; 472 #interrupt-cells = <1>; 473 clocks = <&clkcfg CLK_GPIO2>; 474 gpio-controller; 475 #gpio-cells = <2>; 476 status = "disabled"; 477 }; 478 479 rtc: rtc@20124000 { 480 compatible = "microchip,mpfs-rtc"; 481 reg = <0x0 0x20124000 0x0 0x1000>; 482 interrupt-parent = <&plic>; 483 interrupts = <80>, <81>; 484 clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; 485 clock-names = "rtc", "rtcref"; 486 status = "disabled"; 487 }; 488 489 usb: usb@20201000 { 490 compatible = "microchip,mpfs-musb"; 491 reg = <0x0 0x20201000 0x0 0x1000>; 492 interrupt-parent = <&plic>; 493 interrupts = <86>, <87>; 494 clocks = <&clkcfg CLK_USB>; 495 interrupt-names = "dma","mc"; 496 status = "disabled"; 497 }; 498 499 mbox: mailbox@37020000 { 500 compatible = "microchip,mpfs-mailbox"; 501 reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; 502 interrupt-parent = <&plic>; 503 interrupts = <96>; 504 #mbox-cells = <1>; 505 status = "disabled"; 506 }; 507 }; 508}; 509