1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2020-2021 Microchip Technology Inc */ 3 4/dts-v1/; 5 6#include "mpfs.dtsi" 7#include "mpfs-icicle-kit-fabric.dtsi" 8 9/* Clock frequency (in Hz) of the rtcclk */ 10#define RTCCLK_FREQ 1000000 11 12/ { 13 model = "Microchip PolarFire-SoC Icicle Kit"; 14 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", 15 "microchip,mpfs"; 16 17 aliases { 18 ethernet0 = &mac1; 19 serial0 = &mmuart0; 20 serial1 = &mmuart1; 21 serial2 = &mmuart2; 22 serial3 = &mmuart3; 23 serial4 = &mmuart4; 24 }; 25 26 chosen { 27 stdout-path = "serial1:115200n8"; 28 }; 29 30 cpus { 31 timebase-frequency = <RTCCLK_FREQ>; 32 }; 33 34 ddrc_cache_lo: memory@80000000 { 35 device_type = "memory"; 36 reg = <0x0 0x80000000 0x0 0x2e000000>; 37 status = "okay"; 38 }; 39 40 ddrc_cache_hi: memory@1000000000 { 41 device_type = "memory"; 42 reg = <0x10 0x0 0x0 0x40000000>; 43 status = "okay"; 44 }; 45}; 46 47&core_pwm0 { 48 status = "okay"; 49}; 50 51&gpio2 { 52 interrupts = <53>, <53>, <53>, <53>, 53 <53>, <53>, <53>, <53>, 54 <53>, <53>, <53>, <53>, 55 <53>, <53>, <53>, <53>, 56 <53>, <53>, <53>, <53>, 57 <53>, <53>, <53>, <53>, 58 <53>, <53>, <53>, <53>, 59 <53>, <53>, <53>, <53>; 60 status = "okay"; 61}; 62 63&i2c0 { 64 status = "okay"; 65}; 66 67&i2c1 { 68 status = "okay"; 69}; 70 71&i2c2 { 72 status = "okay"; 73}; 74 75&mac0 { 76 phy-mode = "sgmii"; 77 phy-handle = <&phy0>; 78 status = "okay"; 79}; 80 81&mac1 { 82 phy-mode = "sgmii"; 83 phy-handle = <&phy1>; 84 status = "okay"; 85 86 phy1: ethernet-phy@9 { 87 reg = <9>; 88 ti,fifo-depth = <0x1>; 89 }; 90 91 phy0: ethernet-phy@8 { 92 reg = <8>; 93 ti,fifo-depth = <0x1>; 94 }; 95}; 96 97&mbox { 98 status = "okay"; 99}; 100 101&mmc { 102 bus-width = <4>; 103 disable-wp; 104 cap-sd-highspeed; 105 cap-mmc-highspeed; 106 card-detect-delay = <200>; 107 mmc-ddr-1_8v; 108 mmc-hs200-1_8v; 109 sd-uhs-sdr12; 110 sd-uhs-sdr25; 111 sd-uhs-sdr50; 112 sd-uhs-sdr104; 113 status = "okay"; 114}; 115 116&mmuart1 { 117 status = "okay"; 118}; 119 120&mmuart2 { 121 status = "okay"; 122}; 123 124&mmuart3 { 125 status = "okay"; 126}; 127 128&mmuart4 { 129 status = "okay"; 130}; 131 132&pcie { 133 status = "okay"; 134}; 135 136&qspi { 137 status = "okay"; 138}; 139 140&refclk { 141 clock-frequency = <125000000>; 142}; 143 144&rtc { 145 status = "okay"; 146}; 147 148&spi0 { 149 status = "okay"; 150}; 151 152&spi1 { 153 status = "okay"; 154}; 155 156&syscontroller { 157 status = "okay"; 158}; 159 160&usb { 161 status = "okay"; 162 dr_mode = "host"; 163}; 164