1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2020-2021 Microchip Technology Inc */ 3 4/dts-v1/; 5 6#include "mpfs.dtsi" 7 8/* Clock frequency (in Hz) of the rtcclk */ 9#define RTCCLK_FREQ 1000000 10 11/ { 12 model = "Microchip PolarFire-SoC Icicle Kit"; 13 compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; 14 15 aliases { 16 ethernet0 = &mac1; 17 serial0 = &mmuart0; 18 serial1 = &mmuart1; 19 serial2 = &mmuart2; 20 serial3 = &mmuart3; 21 serial4 = &mmuart4; 22 }; 23 24 chosen { 25 stdout-path = "serial1:115200n8"; 26 }; 27 28 cpus { 29 timebase-frequency = <RTCCLK_FREQ>; 30 }; 31 32 ddrc_cache_lo: memory@80000000 { 33 device_type = "memory"; 34 reg = <0x0 0x80000000 0x0 0x2e000000>; 35 status = "okay"; 36 }; 37 38 ddrc_cache_hi: memory@1000000000 { 39 device_type = "memory"; 40 reg = <0x10 0x0 0x0 0x40000000>; 41 status = "okay"; 42 }; 43}; 44 45&refclk { 46 clock-frequency = <125000000>; 47}; 48 49&mmuart1 { 50 status = "okay"; 51}; 52 53&mmuart2 { 54 status = "okay"; 55}; 56 57&mmuart3 { 58 status = "okay"; 59}; 60 61&mmuart4 { 62 status = "okay"; 63}; 64 65&mmc { 66 status = "okay"; 67 68 bus-width = <4>; 69 disable-wp; 70 cap-sd-highspeed; 71 cap-mmc-highspeed; 72 card-detect-delay = <200>; 73 mmc-ddr-1_8v; 74 mmc-hs200-1_8v; 75 sd-uhs-sdr12; 76 sd-uhs-sdr25; 77 sd-uhs-sdr50; 78 sd-uhs-sdr104; 79}; 80 81&spi0 { 82 status = "okay"; 83}; 84 85&spi1 { 86 status = "okay"; 87}; 88 89&qspi { 90 status = "okay"; 91}; 92 93&i2c0 { 94 status = "okay"; 95}; 96 97&i2c1 { 98 status = "okay"; 99}; 100 101&i2c2 { 102 status = "okay"; 103}; 104 105&mac0 { 106 phy-mode = "sgmii"; 107 phy-handle = <&phy0>; 108}; 109 110&mac1 { 111 status = "okay"; 112 phy-mode = "sgmii"; 113 phy-handle = <&phy1>; 114 phy1: ethernet-phy@9 { 115 reg = <9>; 116 ti,fifo-depth = <0x1>; 117 }; 118 phy0: ethernet-phy@8 { 119 reg = <8>; 120 ti,fifo-depth = <0x1>; 121 }; 122}; 123 124&gpio2 { 125 interrupts = <53>, <53>, <53>, <53>, 126 <53>, <53>, <53>, <53>, 127 <53>, <53>, <53>, <53>, 128 <53>, <53>, <53>, <53>, 129 <53>, <53>, <53>, <53>, 130 <53>, <53>, <53>, <53>, 131 <53>, <53>, <53>, <53>, 132 <53>, <53>, <53>, <53>; 133 status = "okay"; 134}; 135 136&rtc { 137 status = "okay"; 138}; 139 140&usb { 141 status = "okay"; 142 dr_mode = "host"; 143}; 144 145&mbox { 146 status = "okay"; 147}; 148 149&syscontroller { 150 status = "okay"; 151}; 152 153&pcie { 154 status = "okay"; 155}; 156 157&core_pwm0 { 158 status = "okay"; 159}; 160