1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2020-2021 Microchip Technology Inc */
3
4/dts-v1/;
5
6#include "mpfs.dtsi"
7#include "mpfs-icicle-kit-fabric.dtsi"
8
9/* Clock frequency (in Hz) of the rtcclk */
10#define RTCCLK_FREQ		1000000
11
12/ {
13	model = "Microchip PolarFire-SoC Icicle Kit";
14	compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
15
16	aliases {
17		ethernet0 = &mac1;
18		serial0 = &mmuart0;
19		serial1 = &mmuart1;
20		serial2 = &mmuart2;
21		serial3 = &mmuart3;
22		serial4 = &mmuart4;
23	};
24
25	chosen {
26		stdout-path = "serial1:115200n8";
27	};
28
29	cpus {
30		timebase-frequency = <RTCCLK_FREQ>;
31	};
32
33	ddrc_cache_lo: memory@80000000 {
34		device_type = "memory";
35		reg = <0x0 0x80000000 0x0 0x2e000000>;
36		status = "okay";
37	};
38
39	ddrc_cache_hi: memory@1000000000 {
40		device_type = "memory";
41		reg = <0x10 0x0 0x0 0x40000000>;
42		status = "okay";
43	};
44};
45
46&core_pwm0 {
47	status = "okay";
48};
49
50&gpio2 {
51	interrupts = <53>, <53>, <53>, <53>,
52		     <53>, <53>, <53>, <53>,
53		     <53>, <53>, <53>, <53>,
54		     <53>, <53>, <53>, <53>,
55		     <53>, <53>, <53>, <53>,
56		     <53>, <53>, <53>, <53>,
57		     <53>, <53>, <53>, <53>,
58		     <53>, <53>, <53>, <53>;
59	status = "okay";
60};
61
62&i2c0 {
63	status = "okay";
64};
65
66&i2c1 {
67	status = "okay";
68};
69
70&i2c2 {
71	status = "okay";
72};
73
74&mac0 {
75	phy-mode = "sgmii";
76	phy-handle = <&phy0>;
77	status = "okay";
78};
79
80&mac1 {
81	phy-mode = "sgmii";
82	phy-handle = <&phy1>;
83	status = "okay";
84
85	phy1: ethernet-phy@9 {
86		reg = <9>;
87		ti,fifo-depth = <0x1>;
88	};
89
90	phy0: ethernet-phy@8 {
91		reg = <8>;
92		ti,fifo-depth = <0x1>;
93	};
94};
95
96&mbox {
97	status = "okay";
98};
99
100&mmc {
101	bus-width = <4>;
102	disable-wp;
103	cap-sd-highspeed;
104	cap-mmc-highspeed;
105	card-detect-delay = <200>;
106	mmc-ddr-1_8v;
107	mmc-hs200-1_8v;
108	sd-uhs-sdr12;
109	sd-uhs-sdr25;
110	sd-uhs-sdr50;
111	sd-uhs-sdr104;
112	status = "okay";
113};
114
115&mmuart1 {
116	status = "okay";
117};
118
119&mmuart2 {
120	status = "okay";
121};
122
123&mmuart3 {
124	status = "okay";
125};
126
127&mmuart4 {
128	status = "okay";
129};
130
131&pcie {
132	status = "okay";
133};
134
135&qspi {
136	status = "okay";
137};
138
139&refclk {
140	clock-frequency = <125000000>;
141};
142
143&rtc {
144	status = "okay";
145};
146
147&spi0 {
148	status = "okay";
149};
150
151&spi1 {
152	status = "okay";
153};
154
155&syscontroller {
156	status = "okay";
157};
158
159&usb {
160	status = "okay";
161	dr_mode = "host";
162};
163