1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2020-2021 Microchip Technology Inc */ 3 4/dts-v1/; 5 6#include "mpfs.dtsi" 7#include "mpfs-icicle-kit-fabric.dtsi" 8 9/* Clock frequency (in Hz) of the rtcclk */ 10#define RTCCLK_FREQ 1000000 11 12/ { 13 model = "Microchip PolarFire-SoC Icicle Kit"; 14 compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; 15 16 aliases { 17 ethernet0 = &mac1; 18 serial0 = &mmuart0; 19 serial1 = &mmuart1; 20 serial2 = &mmuart2; 21 serial3 = &mmuart3; 22 serial4 = &mmuart4; 23 }; 24 25 chosen { 26 stdout-path = "serial1:115200n8"; 27 }; 28 29 cpus { 30 timebase-frequency = <RTCCLK_FREQ>; 31 }; 32 33 ddrc_cache_lo: memory@80000000 { 34 device_type = "memory"; 35 reg = <0x0 0x80000000 0x0 0x2e000000>; 36 status = "okay"; 37 }; 38 39 ddrc_cache_hi: memory@1000000000 { 40 device_type = "memory"; 41 reg = <0x10 0x0 0x0 0x40000000>; 42 status = "okay"; 43 }; 44}; 45 46&core_pwm0 { 47 status = "okay"; 48}; 49 50&gpio2 { 51 interrupts = <53>, <53>, <53>, <53>, 52 <53>, <53>, <53>, <53>, 53 <53>, <53>, <53>, <53>, 54 <53>, <53>, <53>, <53>, 55 <53>, <53>, <53>, <53>, 56 <53>, <53>, <53>, <53>, 57 <53>, <53>, <53>, <53>, 58 <53>, <53>, <53>, <53>; 59 status = "okay"; 60}; 61 62&i2c0 { 63 status = "okay"; 64}; 65 66&i2c1 { 67 status = "okay"; 68}; 69 70&i2c2 { 71 status = "okay"; 72}; 73 74&mac0 { 75 phy-mode = "sgmii"; 76 phy-handle = <&phy0>; 77 status = "okay"; 78}; 79 80&mac1 { 81 phy-mode = "sgmii"; 82 phy-handle = <&phy1>; 83 status = "okay"; 84 85 phy1: ethernet-phy@9 { 86 reg = <9>; 87 }; 88 89 phy0: ethernet-phy@8 { 90 reg = <8>; 91 }; 92}; 93 94&mbox { 95 status = "okay"; 96}; 97 98&mmc { 99 bus-width = <4>; 100 disable-wp; 101 cap-sd-highspeed; 102 cap-mmc-highspeed; 103 card-detect-delay = <200>; 104 mmc-ddr-1_8v; 105 mmc-hs200-1_8v; 106 sd-uhs-sdr12; 107 sd-uhs-sdr25; 108 sd-uhs-sdr50; 109 sd-uhs-sdr104; 110 status = "okay"; 111}; 112 113&mmuart1 { 114 status = "okay"; 115}; 116 117&mmuart2 { 118 status = "okay"; 119}; 120 121&mmuart3 { 122 status = "okay"; 123}; 124 125&mmuart4 { 126 status = "okay"; 127}; 128 129&pcie { 130 status = "okay"; 131}; 132 133&qspi { 134 status = "okay"; 135}; 136 137&refclk { 138 clock-frequency = <125000000>; 139}; 140 141&rtc { 142 status = "okay"; 143}; 144 145&spi0 { 146 status = "okay"; 147}; 148 149&spi1 { 150 status = "okay"; 151}; 152 153&syscontroller { 154 status = "okay"; 155}; 156 157&usb { 158 status = "okay"; 159 dr_mode = "host"; 160}; 161