1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2020-2021 Microchip Technology Inc */ 3 4/dts-v1/; 5 6#include "mpfs.dtsi" 7#include "mpfs-icicle-kit-fabric.dtsi" 8 9/* Clock frequency (in Hz) of the rtcclk */ 10#define RTCCLK_FREQ 1000000 11 12/ { 13 model = "Microchip PolarFire-SoC Icicle Kit"; 14 compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; 15 16 aliases { 17 ethernet0 = &mac1; 18 serial0 = &mmuart0; 19 serial1 = &mmuart1; 20 serial2 = &mmuart2; 21 serial3 = &mmuart3; 22 serial4 = &mmuart4; 23 }; 24 25 chosen { 26 stdout-path = "serial1:115200n8"; 27 }; 28 29 cpus { 30 timebase-frequency = <RTCCLK_FREQ>; 31 }; 32 33 ddrc_cache_lo: memory@80000000 { 34 device_type = "memory"; 35 reg = <0x0 0x80000000 0x0 0x2e000000>; 36 status = "okay"; 37 }; 38 39 ddrc_cache_hi: memory@1000000000 { 40 device_type = "memory"; 41 reg = <0x10 0x0 0x0 0x40000000>; 42 status = "okay"; 43 }; 44}; 45 46&refclk { 47 clock-frequency = <125000000>; 48}; 49 50&mmuart1 { 51 status = "okay"; 52}; 53 54&mmuart2 { 55 status = "okay"; 56}; 57 58&mmuart3 { 59 status = "okay"; 60}; 61 62&mmuart4 { 63 status = "okay"; 64}; 65 66&mmc { 67 status = "okay"; 68 69 bus-width = <4>; 70 disable-wp; 71 cap-sd-highspeed; 72 cap-mmc-highspeed; 73 card-detect-delay = <200>; 74 mmc-ddr-1_8v; 75 mmc-hs200-1_8v; 76 sd-uhs-sdr12; 77 sd-uhs-sdr25; 78 sd-uhs-sdr50; 79 sd-uhs-sdr104; 80}; 81 82&spi0 { 83 status = "okay"; 84}; 85 86&spi1 { 87 status = "okay"; 88}; 89 90&qspi { 91 status = "okay"; 92}; 93 94&i2c0 { 95 status = "okay"; 96}; 97 98&i2c1 { 99 status = "okay"; 100}; 101 102&i2c2 { 103 status = "okay"; 104}; 105 106&mac0 { 107 phy-mode = "sgmii"; 108 phy-handle = <&phy0>; 109}; 110 111&mac1 { 112 status = "okay"; 113 phy-mode = "sgmii"; 114 phy-handle = <&phy1>; 115 phy1: ethernet-phy@9 { 116 reg = <9>; 117 ti,fifo-depth = <0x1>; 118 }; 119 phy0: ethernet-phy@8 { 120 reg = <8>; 121 ti,fifo-depth = <0x1>; 122 }; 123}; 124 125&gpio2 { 126 interrupts = <53>, <53>, <53>, <53>, 127 <53>, <53>, <53>, <53>, 128 <53>, <53>, <53>, <53>, 129 <53>, <53>, <53>, <53>, 130 <53>, <53>, <53>, <53>, 131 <53>, <53>, <53>, <53>, 132 <53>, <53>, <53>, <53>, 133 <53>, <53>, <53>, <53>; 134 status = "okay"; 135}; 136 137&rtc { 138 status = "okay"; 139}; 140 141&usb { 142 status = "okay"; 143 dr_mode = "host"; 144}; 145 146&mbox { 147 status = "okay"; 148}; 149 150&syscontroller { 151 status = "okay"; 152}; 153 154&pcie { 155 status = "okay"; 156}; 157 158&core_pwm0 { 159 status = "okay"; 160}; 161