1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> 4 * Copyright (C) 2020 Western Digital Corporation or its affiliates. 5 */ 6#include <dt-bindings/clock/k210-clk.h> 7#include <dt-bindings/pinctrl/k210-fpioa.h> 8#include <dt-bindings/reset/k210-rst.h> 9 10/ { 11 /* 12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits 13 * wide, and the upper half of all addresses is ignored. 14 */ 15 #address-cells = <1>; 16 #size-cells = <1>; 17 compatible = "canaan,kendryte-k210"; 18 19 aliases { 20 serial0 = &uarths0; 21 serial1 = &uart1; 22 serial2 = &uart2; 23 serial3 = &uart3; 24 }; 25 26 /* 27 * The K210 has an sv39 MMU following the privileged specification v1.9. 28 * Since this is a non-ratified draft specification, the kernel does not 29 * support it and the K210 support enabled only for the !MMU case. 30 * Be consistent with this by setting the CPUs MMU type to "none". 31 */ 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 timebase-frequency = <7800000>; 36 cpu0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "canaan,k210", "riscv"; 39 reg = <0>; 40 riscv,isa = "rv64imafdc"; 41 mmu-type = "riscv,none"; 42 i-cache-block-size = <64>; 43 i-cache-size = <0x8000>; 44 d-cache-block-size = <64>; 45 d-cache-size = <0x8000>; 46 cpu0_intc: interrupt-controller { 47 #interrupt-cells = <1>; 48 interrupt-controller; 49 compatible = "riscv,cpu-intc"; 50 }; 51 }; 52 cpu1: cpu@1 { 53 device_type = "cpu"; 54 compatible = "canaan,k210", "riscv"; 55 reg = <1>; 56 riscv,isa = "rv64imafdc"; 57 mmu-type = "riscv,none"; 58 i-cache-block-size = <64>; 59 i-cache-size = <0x8000>; 60 d-cache-block-size = <64>; 61 d-cache-size = <0x8000>; 62 cpu1_intc: interrupt-controller { 63 #interrupt-cells = <1>; 64 interrupt-controller; 65 compatible = "riscv,cpu-intc"; 66 }; 67 }; 68 69 cpu-map { 70 cluster0 { 71 core0 { 72 cpu = <&cpu0>; 73 }; 74 75 core1 { 76 cpu = <&cpu1>; 77 }; 78 }; 79 }; 80 }; 81 82 sram: memory@80000000 { 83 device_type = "memory"; 84 compatible = "canaan,k210-sram"; 85 reg = <0x80000000 0x400000>, 86 <0x80400000 0x200000>, 87 <0x80600000 0x200000>; 88 reg-names = "sram0", "sram1", "aisram"; 89 clocks = <&sysclk K210_CLK_SRAM0>, 90 <&sysclk K210_CLK_SRAM1>, 91 <&sysclk K210_CLK_AI>; 92 clock-names = "sram0", "sram1", "aisram"; 93 }; 94 95 clocks { 96 in0: oscillator { 97 compatible = "fixed-clock"; 98 #clock-cells = <0>; 99 clock-frequency = <26000000>; 100 }; 101 }; 102 103 soc { 104 #address-cells = <1>; 105 #size-cells = <1>; 106 compatible = "simple-bus"; 107 ranges; 108 interrupt-parent = <&plic0>; 109 110 rom0: nvmem@1000 { 111 reg = <0x1000 0x1000>; 112 read-only; 113 }; 114 115 clint0: timer@2000000 { 116 compatible = "canaan,k210-clint", "sifive,clint0"; 117 reg = <0x2000000 0xC000>; 118 interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 119 &cpu1_intc 3 &cpu1_intc 7>; 120 }; 121 122 plic0: interrupt-controller@c000000 { 123 #interrupt-cells = <1>; 124 #address-cells = <0>; 125 compatible = "canaan,k210-plic", "sifive,plic-1.0.0"; 126 reg = <0xC000000 0x4000000>; 127 interrupt-controller; 128 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 129 <&cpu1_intc 11>, <&cpu1_intc 9>; 130 riscv,ndev = <65>; 131 }; 132 133 uarths0: serial@38000000 { 134 compatible = "canaan,k210-uarths", "sifive,uart0"; 135 reg = <0x38000000 0x1000>; 136 interrupts = <33>; 137 clocks = <&sysclk K210_CLK_CPU>; 138 }; 139 140 gpio0: gpio-controller@38001000 { 141 #interrupt-cells = <2>; 142 #gpio-cells = <2>; 143 compatible = "canaan,k210-gpiohs", "sifive,gpio0"; 144 reg = <0x38001000 0x1000>; 145 interrupt-controller; 146 interrupts = <34 35 36 37 38 39 40 41 147 42 43 44 45 46 47 48 49 148 50 51 52 53 54 55 56 57 149 58 59 60 61 62 63 64 65>; 150 gpio-controller; 151 ngpios = <32>; 152 }; 153 154 dmac0: dma-controller@50000000 { 155 compatible = "snps,axi-dma-1.01a"; 156 reg = <0x50000000 0x1000>; 157 interrupts = <27 28 29 30 31 32>; 158 #dma-cells = <1>; 159 clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; 160 clock-names = "core-clk", "cfgr-clk"; 161 resets = <&sysrst K210_RST_DMA>; 162 dma-channels = <6>; 163 snps,dma-masters = <2>; 164 snps,priority = <0 1 2 3 4 5>; 165 snps,data-width = <5>; 166 snps,block-size = <0x200000 0x200000 0x200000 167 0x200000 0x200000 0x200000>; 168 snps,axi-max-burst-len = <256>; 169 }; 170 171 apb0: bus@50200000 { 172 #address-cells = <1>; 173 #size-cells = <1>; 174 compatible = "simple-pm-bus"; 175 ranges; 176 clocks = <&sysclk K210_CLK_APB0>; 177 178 gpio1: gpio@50200000 { 179 #address-cells = <1>; 180 #size-cells = <0>; 181 compatible = "snps,dw-apb-gpio"; 182 reg = <0x50200000 0x80>; 183 clocks = <&sysclk K210_CLK_APB0>, 184 <&sysclk K210_CLK_GPIO>; 185 clock-names = "bus", "db"; 186 resets = <&sysrst K210_RST_GPIO>; 187 188 gpio1_0: gpio-port@0 { 189 #gpio-cells = <2>; 190 #interrupt-cells = <2>; 191 compatible = "snps,dw-apb-gpio-port"; 192 reg = <0>; 193 interrupt-controller; 194 interrupts = <23>; 195 gpio-controller; 196 ngpios = <8>; 197 }; 198 }; 199 200 uart1: serial@50210000 { 201 compatible = "snps,dw-apb-uart"; 202 reg = <0x50210000 0x100>; 203 interrupts = <11>; 204 clocks = <&sysclk K210_CLK_UART1>, 205 <&sysclk K210_CLK_APB0>; 206 clock-names = "baudclk", "apb_pclk"; 207 resets = <&sysrst K210_RST_UART1>; 208 reg-io-width = <4>; 209 reg-shift = <2>; 210 dcd-override; 211 dsr-override; 212 cts-override; 213 ri-override; 214 }; 215 216 uart2: serial@50220000 { 217 compatible = "snps,dw-apb-uart"; 218 reg = <0x50220000 0x100>; 219 interrupts = <12>; 220 clocks = <&sysclk K210_CLK_UART2>, 221 <&sysclk K210_CLK_APB0>; 222 clock-names = "baudclk", "apb_pclk"; 223 resets = <&sysrst K210_RST_UART2>; 224 reg-io-width = <4>; 225 reg-shift = <2>; 226 dcd-override; 227 dsr-override; 228 cts-override; 229 ri-override; 230 }; 231 232 uart3: serial@50230000 { 233 compatible = "snps,dw-apb-uart"; 234 reg = <0x50230000 0x100>; 235 interrupts = <13>; 236 clocks = <&sysclk K210_CLK_UART3>, 237 <&sysclk K210_CLK_APB0>; 238 clock-names = "baudclk", "apb_pclk"; 239 resets = <&sysrst K210_RST_UART3>; 240 reg-io-width = <4>; 241 reg-shift = <2>; 242 dcd-override; 243 dsr-override; 244 cts-override; 245 ri-override; 246 }; 247 248 spi2: spi@50240000 { 249 compatible = "canaan,k210-spi"; 250 spi-slave; 251 reg = <0x50240000 0x100>; 252 #address-cells = <0>; 253 #size-cells = <0>; 254 interrupts = <3>; 255 clocks = <&sysclk K210_CLK_SPI2>, 256 <&sysclk K210_CLK_APB0>; 257 clock-names = "ssi_clk", "pclk"; 258 resets = <&sysrst K210_RST_SPI2>; 259 spi-max-frequency = <25000000>; 260 }; 261 262 i2s0: i2s@50250000 { 263 compatible = "snps,designware-i2s"; 264 reg = <0x50250000 0x200>; 265 interrupts = <5>; 266 clocks = <&sysclk K210_CLK_I2S0>; 267 clock-names = "i2sclk"; 268 resets = <&sysrst K210_RST_I2S0>; 269 }; 270 271 i2s1: i2s@50260000 { 272 compatible = "snps,designware-i2s"; 273 reg = <0x50260000 0x200>; 274 interrupts = <6>; 275 clocks = <&sysclk K210_CLK_I2S1>; 276 clock-names = "i2sclk"; 277 resets = <&sysrst K210_RST_I2S1>; 278 }; 279 280 i2s2: i2s@50270000 { 281 compatible = "snps,designware-i2s"; 282 reg = <0x50270000 0x200>; 283 interrupts = <7>; 284 clocks = <&sysclk K210_CLK_I2S2>; 285 clock-names = "i2sclk"; 286 resets = <&sysrst K210_RST_I2S2>; 287 }; 288 289 i2c0: i2c@50280000 { 290 compatible = "snps,designware-i2c"; 291 reg = <0x50280000 0x100>; 292 interrupts = <8>; 293 clocks = <&sysclk K210_CLK_I2C0>, 294 <&sysclk K210_CLK_APB0>; 295 clock-names = "ref", "pclk"; 296 resets = <&sysrst K210_RST_I2C0>; 297 }; 298 299 i2c1: i2c@50290000 { 300 compatible = "snps,designware-i2c"; 301 reg = <0x50290000 0x100>; 302 interrupts = <9>; 303 clocks = <&sysclk K210_CLK_I2C1>, 304 <&sysclk K210_CLK_APB0>; 305 clock-names = "ref", "pclk"; 306 resets = <&sysrst K210_RST_I2C1>; 307 }; 308 309 i2c2: i2c@502a0000 { 310 compatible = "snps,designware-i2c"; 311 reg = <0x502A0000 0x100>; 312 interrupts = <10>; 313 clocks = <&sysclk K210_CLK_I2C2>, 314 <&sysclk K210_CLK_APB0>; 315 clock-names = "ref", "pclk"; 316 resets = <&sysrst K210_RST_I2C2>; 317 }; 318 319 fpioa: pinmux@502b0000 { 320 compatible = "canaan,k210-fpioa"; 321 reg = <0x502B0000 0x100>; 322 clocks = <&sysclk K210_CLK_FPIOA>, 323 <&sysclk K210_CLK_APB0>; 324 clock-names = "ref", "pclk"; 325 resets = <&sysrst K210_RST_FPIOA>; 326 canaan,k210-sysctl-power = <&sysctl 108>; 327 }; 328 329 timer0: timer@502d0000 { 330 compatible = "snps,dw-apb-timer"; 331 reg = <0x502D0000 0x100>; 332 interrupts = <14 15>; 333 clocks = <&sysclk K210_CLK_TIMER0>, 334 <&sysclk K210_CLK_APB0>; 335 clock-names = "timer", "pclk"; 336 resets = <&sysrst K210_RST_TIMER0>; 337 }; 338 339 timer1: timer@502e0000 { 340 compatible = "snps,dw-apb-timer"; 341 reg = <0x502E0000 0x100>; 342 interrupts = <16 17>; 343 clocks = <&sysclk K210_CLK_TIMER1>, 344 <&sysclk K210_CLK_APB0>; 345 clock-names = "timer", "pclk"; 346 resets = <&sysrst K210_RST_TIMER1>; 347 }; 348 349 timer2: timer@502f0000 { 350 compatible = "snps,dw-apb-timer"; 351 reg = <0x502F0000 0x100>; 352 interrupts = <18 19>; 353 clocks = <&sysclk K210_CLK_TIMER2>, 354 <&sysclk K210_CLK_APB0>; 355 clock-names = "timer", "pclk"; 356 resets = <&sysrst K210_RST_TIMER2>; 357 }; 358 }; 359 360 apb1: bus@50400000 { 361 #address-cells = <1>; 362 #size-cells = <1>; 363 compatible = "simple-pm-bus"; 364 ranges; 365 clocks = <&sysclk K210_CLK_APB1>; 366 367 wdt0: watchdog@50400000 { 368 compatible = "snps,dw-wdt"; 369 reg = <0x50400000 0x100>; 370 interrupts = <21>; 371 clocks = <&sysclk K210_CLK_WDT0>, 372 <&sysclk K210_CLK_APB1>; 373 clock-names = "tclk", "pclk"; 374 resets = <&sysrst K210_RST_WDT0>; 375 }; 376 377 wdt1: watchdog@50410000 { 378 compatible = "snps,dw-wdt"; 379 reg = <0x50410000 0x100>; 380 interrupts = <22>; 381 clocks = <&sysclk K210_CLK_WDT1>, 382 <&sysclk K210_CLK_APB1>; 383 clock-names = "tclk", "pclk"; 384 resets = <&sysrst K210_RST_WDT1>; 385 }; 386 387 sysctl: syscon@50440000 { 388 compatible = "canaan,k210-sysctl", 389 "syscon", "simple-mfd"; 390 reg = <0x50440000 0x100>; 391 clocks = <&sysclk K210_CLK_APB1>; 392 clock-names = "pclk"; 393 394 sysclk: clock-controller { 395 #clock-cells = <1>; 396 compatible = "canaan,k210-clk"; 397 clocks = <&in0>; 398 }; 399 400 sysrst: reset-controller { 401 compatible = "canaan,k210-rst"; 402 #reset-cells = <1>; 403 }; 404 405 reboot: syscon-reboot { 406 compatible = "syscon-reboot"; 407 regmap = <&sysctl>; 408 offset = <48>; 409 mask = <1>; 410 value = <1>; 411 }; 412 }; 413 }; 414 415 apb2: bus@52000000 { 416 #address-cells = <1>; 417 #size-cells = <1>; 418 compatible = "simple-pm-bus"; 419 ranges; 420 clocks = <&sysclk K210_CLK_APB2>; 421 422 spi0: spi@52000000 { 423 #address-cells = <1>; 424 #size-cells = <0>; 425 compatible = "canaan,k210-spi"; 426 reg = <0x52000000 0x100>; 427 interrupts = <1>; 428 clocks = <&sysclk K210_CLK_SPI0>, 429 <&sysclk K210_CLK_APB2>; 430 clock-names = "ssi_clk", "pclk"; 431 resets = <&sysrst K210_RST_SPI0>; 432 reset-names = "spi"; 433 spi-max-frequency = <25000000>; 434 num-cs = <4>; 435 reg-io-width = <4>; 436 }; 437 438 spi1: spi@53000000 { 439 #address-cells = <1>; 440 #size-cells = <0>; 441 compatible = "canaan,k210-spi"; 442 reg = <0x53000000 0x100>; 443 interrupts = <2>; 444 clocks = <&sysclk K210_CLK_SPI1>, 445 <&sysclk K210_CLK_APB2>; 446 clock-names = "ssi_clk", "pclk"; 447 resets = <&sysrst K210_RST_SPI1>; 448 reset-names = "spi"; 449 spi-max-frequency = <25000000>; 450 num-cs = <4>; 451 reg-io-width = <4>; 452 }; 453 454 spi3: spi@54000000 { 455 #address-cells = <1>; 456 #size-cells = <0>; 457 compatible = "snps,dwc-ssi-1.01a"; 458 reg = <0x54000000 0x200>; 459 interrupts = <4>; 460 clocks = <&sysclk K210_CLK_SPI3>, 461 <&sysclk K210_CLK_APB2>; 462 clock-names = "ssi_clk", "pclk"; 463 resets = <&sysrst K210_RST_SPI3>; 464 reset-names = "spi"; 465 /* Could possibly go up to 200 MHz */ 466 spi-max-frequency = <100000000>; 467 num-cs = <4>; 468 reg-io-width = <4>; 469 }; 470 }; 471 }; 472}; 473