1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> 4 * Copyright (C) 2020 Western Digital Corporation or its affiliates. 5 */ 6#include <dt-bindings/clock/k210-clk.h> 7#include <dt-bindings/pinctrl/k210-fpioa.h> 8#include <dt-bindings/reset/k210-rst.h> 9 10/ { 11 /* 12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits 13 * wide, and the upper half of all addresses is ignored. 14 */ 15 #address-cells = <1>; 16 #size-cells = <1>; 17 compatible = "canaan,kendryte-k210"; 18 19 aliases { 20 serial0 = &uarths0; 21 serial1 = &uart1; 22 serial2 = &uart2; 23 serial3 = &uart3; 24 }; 25 26 /* 27 * The K210 has an sv39 MMU following the privileged specification v1.9. 28 * Since this is a non-ratified draft specification, the kernel does not 29 * support it and the K210 support enabled only for the !MMU case. 30 * Be consistent with this by setting the CPUs MMU type to "none". 31 */ 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 timebase-frequency = <7800000>; 36 cpu0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "canaan,k210", "riscv"; 39 reg = <0>; 40 riscv,isa = "rv64imafdc"; 41 mmu-type = "riscv,none"; 42 i-cache-block-size = <64>; 43 i-cache-size = <0x8000>; 44 d-cache-block-size = <64>; 45 d-cache-size = <0x8000>; 46 cpu0_intc: interrupt-controller { 47 #interrupt-cells = <1>; 48 interrupt-controller; 49 compatible = "riscv,cpu-intc"; 50 }; 51 }; 52 cpu1: cpu@1 { 53 device_type = "cpu"; 54 compatible = "canaan,k210", "riscv"; 55 reg = <1>; 56 riscv,isa = "rv64imafdc"; 57 mmu-type = "riscv,none"; 58 i-cache-block-size = <64>; 59 i-cache-size = <0x8000>; 60 d-cache-block-size = <64>; 61 d-cache-size = <0x8000>; 62 cpu1_intc: interrupt-controller { 63 #interrupt-cells = <1>; 64 interrupt-controller; 65 compatible = "riscv,cpu-intc"; 66 }; 67 }; 68 }; 69 70 sram: memory@80000000 { 71 device_type = "memory"; 72 reg = <0x80000000 0x400000>, /* sram0 4 MiB */ 73 <0x80400000 0x200000>, /* sram1 2 MiB */ 74 <0x80600000 0x200000>; /* aisram 2 MiB */ 75 }; 76 77 sram_controller: memory-controller { 78 compatible = "canaan,k210-sram"; 79 clocks = <&sysclk K210_CLK_SRAM0>, 80 <&sysclk K210_CLK_SRAM1>, 81 <&sysclk K210_CLK_AI>; 82 clock-names = "sram0", "sram1", "aisram"; 83 }; 84 85 clocks { 86 in0: oscillator { 87 compatible = "fixed-clock"; 88 #clock-cells = <0>; 89 clock-frequency = <26000000>; 90 }; 91 }; 92 93 soc { 94 #address-cells = <1>; 95 #size-cells = <1>; 96 compatible = "simple-bus"; 97 ranges; 98 interrupt-parent = <&plic0>; 99 100 rom0: nvmem@1000 { 101 reg = <0x1000 0x1000>; 102 read-only; 103 }; 104 105 clint0: timer@2000000 { 106 compatible = "canaan,k210-clint", "sifive,clint0"; 107 reg = <0x2000000 0xC000>; 108 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 109 <&cpu1_intc 3>, <&cpu1_intc 7>; 110 }; 111 112 plic0: interrupt-controller@c000000 { 113 #interrupt-cells = <1>; 114 #address-cells = <0>; 115 compatible = "canaan,k210-plic", "sifive,plic-1.0.0"; 116 reg = <0xC000000 0x4000000>; 117 interrupt-controller; 118 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 119 <&cpu1_intc 11>, <&cpu1_intc 9>; 120 riscv,ndev = <65>; 121 }; 122 123 uarths0: serial@38000000 { 124 compatible = "canaan,k210-uarths", "sifive,uart0"; 125 reg = <0x38000000 0x1000>; 126 interrupts = <33>; 127 clocks = <&sysclk K210_CLK_CPU>; 128 }; 129 130 gpio0: gpio-controller@38001000 { 131 #interrupt-cells = <2>; 132 #gpio-cells = <2>; 133 compatible = "canaan,k210-gpiohs", "sifive,gpio0"; 134 reg = <0x38001000 0x1000>; 135 interrupt-controller; 136 interrupts = <34>, <35>, <36>, <37>, <38>, <39>, <40>, 137 <41>, <42>, <43>, <44>, <45>, <46>, <47>, 138 <48>, <49>, <50>, <51>, <52>, <53>, <54>, 139 <55>, <56>, <57>, <58>, <59>, <60>, <61>, 140 <62>, <63>, <64>, <65>; 141 gpio-controller; 142 ngpios = <32>; 143 }; 144 145 dmac0: dma-controller@50000000 { 146 compatible = "snps,axi-dma-1.01a"; 147 reg = <0x50000000 0x1000>; 148 interrupts = <27>, <28>, <29>, <30>, <31>, <32>; 149 #dma-cells = <1>; 150 clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; 151 clock-names = "core-clk", "cfgr-clk"; 152 resets = <&sysrst K210_RST_DMA>; 153 dma-channels = <6>; 154 snps,dma-masters = <2>; 155 snps,priority = <0 1 2 3 4 5>; 156 snps,data-width = <5>; 157 snps,block-size = <0x200000 0x200000 0x200000 158 0x200000 0x200000 0x200000>; 159 snps,axi-max-burst-len = <256>; 160 }; 161 162 apb0: bus@50200000 { 163 #address-cells = <1>; 164 #size-cells = <1>; 165 compatible = "simple-pm-bus"; 166 ranges = <0x50200000 0x50200000 0x200000>; 167 clocks = <&sysclk K210_CLK_APB0>; 168 169 gpio1: gpio@50200000 { 170 #address-cells = <1>; 171 #size-cells = <0>; 172 compatible = "snps,dw-apb-gpio"; 173 reg = <0x50200000 0x80>; 174 clocks = <&sysclk K210_CLK_APB0>, 175 <&sysclk K210_CLK_GPIO>; 176 clock-names = "bus", "db"; 177 resets = <&sysrst K210_RST_GPIO>; 178 179 gpio1_0: gpio-port@0 { 180 #gpio-cells = <2>; 181 #interrupt-cells = <2>; 182 compatible = "snps,dw-apb-gpio-port"; 183 reg = <0>; 184 interrupt-controller; 185 interrupts = <23>; 186 gpio-controller; 187 ngpios = <8>; 188 }; 189 }; 190 191 uart1: serial@50210000 { 192 compatible = "snps,dw-apb-uart"; 193 reg = <0x50210000 0x100>; 194 interrupts = <11>; 195 clocks = <&sysclk K210_CLK_UART1>, 196 <&sysclk K210_CLK_APB0>; 197 clock-names = "baudclk", "apb_pclk"; 198 resets = <&sysrst K210_RST_UART1>; 199 reg-io-width = <4>; 200 reg-shift = <2>; 201 dcd-override; 202 dsr-override; 203 cts-override; 204 ri-override; 205 }; 206 207 uart2: serial@50220000 { 208 compatible = "snps,dw-apb-uart"; 209 reg = <0x50220000 0x100>; 210 interrupts = <12>; 211 clocks = <&sysclk K210_CLK_UART2>, 212 <&sysclk K210_CLK_APB0>; 213 clock-names = "baudclk", "apb_pclk"; 214 resets = <&sysrst K210_RST_UART2>; 215 reg-io-width = <4>; 216 reg-shift = <2>; 217 dcd-override; 218 dsr-override; 219 cts-override; 220 ri-override; 221 }; 222 223 uart3: serial@50230000 { 224 compatible = "snps,dw-apb-uart"; 225 reg = <0x50230000 0x100>; 226 interrupts = <13>; 227 clocks = <&sysclk K210_CLK_UART3>, 228 <&sysclk K210_CLK_APB0>; 229 clock-names = "baudclk", "apb_pclk"; 230 resets = <&sysrst K210_RST_UART3>; 231 reg-io-width = <4>; 232 reg-shift = <2>; 233 dcd-override; 234 dsr-override; 235 cts-override; 236 ri-override; 237 }; 238 239 spi2: spi@50240000 { 240 compatible = "canaan,k210-spi"; 241 spi-slave; 242 reg = <0x50240000 0x100>; 243 #address-cells = <0>; 244 #size-cells = <0>; 245 interrupts = <3>; 246 clocks = <&sysclk K210_CLK_SPI2>, 247 <&sysclk K210_CLK_APB0>; 248 clock-names = "ssi_clk", "pclk"; 249 resets = <&sysrst K210_RST_SPI2>; 250 spi-max-frequency = <25000000>; 251 }; 252 253 i2s0: i2s@50250000 { 254 compatible = "canaan,k210-i2s", "snps,designware-i2s"; 255 reg = <0x50250000 0x200>; 256 interrupts = <5>; 257 clocks = <&sysclk K210_CLK_I2S0>; 258 clock-names = "i2sclk"; 259 resets = <&sysrst K210_RST_I2S0>; 260 }; 261 262 i2s1: i2s@50260000 { 263 compatible = "canaan,k210-i2s", "snps,designware-i2s"; 264 reg = <0x50260000 0x200>; 265 interrupts = <6>; 266 clocks = <&sysclk K210_CLK_I2S1>; 267 clock-names = "i2sclk"; 268 resets = <&sysrst K210_RST_I2S1>; 269 }; 270 271 i2s2: i2s@50270000 { 272 compatible = "canaan,k210-i2s", "snps,designware-i2s"; 273 reg = <0x50270000 0x200>; 274 interrupts = <7>; 275 clocks = <&sysclk K210_CLK_I2S2>; 276 clock-names = "i2sclk"; 277 resets = <&sysrst K210_RST_I2S2>; 278 }; 279 280 i2c0: i2c@50280000 { 281 compatible = "snps,designware-i2c"; 282 reg = <0x50280000 0x100>; 283 interrupts = <8>; 284 clocks = <&sysclk K210_CLK_I2C0>, 285 <&sysclk K210_CLK_APB0>; 286 clock-names = "ref", "pclk"; 287 resets = <&sysrst K210_RST_I2C0>; 288 }; 289 290 i2c1: i2c@50290000 { 291 compatible = "snps,designware-i2c"; 292 reg = <0x50290000 0x100>; 293 interrupts = <9>; 294 clocks = <&sysclk K210_CLK_I2C1>, 295 <&sysclk K210_CLK_APB0>; 296 clock-names = "ref", "pclk"; 297 resets = <&sysrst K210_RST_I2C1>; 298 }; 299 300 i2c2: i2c@502a0000 { 301 compatible = "snps,designware-i2c"; 302 reg = <0x502A0000 0x100>; 303 interrupts = <10>; 304 clocks = <&sysclk K210_CLK_I2C2>, 305 <&sysclk K210_CLK_APB0>; 306 clock-names = "ref", "pclk"; 307 resets = <&sysrst K210_RST_I2C2>; 308 }; 309 310 fpioa: pinmux@502b0000 { 311 compatible = "canaan,k210-fpioa"; 312 reg = <0x502B0000 0x100>; 313 clocks = <&sysclk K210_CLK_FPIOA>, 314 <&sysclk K210_CLK_APB0>; 315 clock-names = "ref", "pclk"; 316 resets = <&sysrst K210_RST_FPIOA>; 317 canaan,k210-sysctl-power = <&sysctl 108>; 318 }; 319 320 timer0: timer@502d0000 { 321 compatible = "snps,dw-apb-timer"; 322 reg = <0x502D0000 0x14>; 323 interrupts = <14>; 324 clocks = <&sysclk K210_CLK_TIMER0>, 325 <&sysclk K210_CLK_APB0>; 326 clock-names = "timer", "pclk"; 327 resets = <&sysrst K210_RST_TIMER0>; 328 }; 329 330 timer1: timer@502d0014 { 331 compatible = "snps,dw-apb-timer"; 332 reg = <0x502D0014 0x14>; 333 interrupts = <15>; 334 clocks = <&sysclk K210_CLK_TIMER0>, 335 <&sysclk K210_CLK_APB0>; 336 clock-names = "timer", "pclk"; 337 resets = <&sysrst K210_RST_TIMER0>; 338 }; 339 340 timer2: timer@502e0000 { 341 compatible = "snps,dw-apb-timer"; 342 reg = <0x502E0000 0x14>; 343 interrupts = <16>; 344 clocks = <&sysclk K210_CLK_TIMER1>, 345 <&sysclk K210_CLK_APB0>; 346 clock-names = "timer", "pclk"; 347 resets = <&sysrst K210_RST_TIMER1>; 348 }; 349 350 timer3: timer@502e0014 { 351 compatible = "snps,dw-apb-timer"; 352 reg = <0x502E0014 0x114>; 353 interrupts = <17>; 354 clocks = <&sysclk K210_CLK_TIMER1>, 355 <&sysclk K210_CLK_APB0>; 356 clock-names = "timer", "pclk"; 357 resets = <&sysrst K210_RST_TIMER1>; 358 }; 359 360 timer4: timer@502f0000 { 361 compatible = "snps,dw-apb-timer"; 362 reg = <0x502F0000 0x14>; 363 interrupts = <18>; 364 clocks = <&sysclk K210_CLK_TIMER2>, 365 <&sysclk K210_CLK_APB0>; 366 clock-names = "timer", "pclk"; 367 resets = <&sysrst K210_RST_TIMER2>; 368 }; 369 370 timer5: timer@502f0014 { 371 compatible = "snps,dw-apb-timer"; 372 reg = <0x502F0014 0x14>; 373 interrupts = <19>; 374 clocks = <&sysclk K210_CLK_TIMER2>, 375 <&sysclk K210_CLK_APB0>; 376 clock-names = "timer", "pclk"; 377 resets = <&sysrst K210_RST_TIMER2>; 378 }; 379 }; 380 381 apb1: bus@50400000 { 382 #address-cells = <1>; 383 #size-cells = <1>; 384 compatible = "simple-pm-bus"; 385 ranges = <0x50400000 0x50400000 0x40100>; 386 clocks = <&sysclk K210_CLK_APB1>; 387 388 wdt0: watchdog@50400000 { 389 compatible = "snps,dw-wdt"; 390 reg = <0x50400000 0x100>; 391 interrupts = <21>; 392 clocks = <&sysclk K210_CLK_WDT0>, 393 <&sysclk K210_CLK_APB1>; 394 clock-names = "tclk", "pclk"; 395 resets = <&sysrst K210_RST_WDT0>; 396 }; 397 398 wdt1: watchdog@50410000 { 399 compatible = "snps,dw-wdt"; 400 reg = <0x50410000 0x100>; 401 interrupts = <22>; 402 clocks = <&sysclk K210_CLK_WDT1>, 403 <&sysclk K210_CLK_APB1>; 404 clock-names = "tclk", "pclk"; 405 resets = <&sysrst K210_RST_WDT1>; 406 }; 407 408 sysctl: syscon@50440000 { 409 compatible = "canaan,k210-sysctl", 410 "syscon", "simple-mfd"; 411 reg = <0x50440000 0x100>; 412 clocks = <&sysclk K210_CLK_APB1>; 413 clock-names = "pclk"; 414 415 sysclk: clock-controller { 416 #clock-cells = <1>; 417 compatible = "canaan,k210-clk"; 418 clocks = <&in0>; 419 }; 420 421 sysrst: reset-controller { 422 compatible = "canaan,k210-rst"; 423 #reset-cells = <1>; 424 }; 425 426 reboot: syscon-reboot { 427 compatible = "syscon-reboot"; 428 regmap = <&sysctl>; 429 offset = <48>; 430 mask = <1>; 431 value = <1>; 432 }; 433 }; 434 }; 435 436 apb2: bus@52000000 { 437 #address-cells = <1>; 438 #size-cells = <1>; 439 compatible = "simple-pm-bus"; 440 ranges = <0x52000000 0x52000000 0x2000200>; 441 clocks = <&sysclk K210_CLK_APB2>; 442 443 spi0: spi@52000000 { 444 #address-cells = <1>; 445 #size-cells = <0>; 446 compatible = "canaan,k210-spi"; 447 reg = <0x52000000 0x100>; 448 interrupts = <1>; 449 clocks = <&sysclk K210_CLK_SPI0>, 450 <&sysclk K210_CLK_APB2>; 451 clock-names = "ssi_clk", "pclk"; 452 resets = <&sysrst K210_RST_SPI0>; 453 reset-names = "spi"; 454 num-cs = <4>; 455 reg-io-width = <4>; 456 }; 457 458 spi1: spi@53000000 { 459 #address-cells = <1>; 460 #size-cells = <0>; 461 compatible = "canaan,k210-spi"; 462 reg = <0x53000000 0x100>; 463 interrupts = <2>; 464 clocks = <&sysclk K210_CLK_SPI1>, 465 <&sysclk K210_CLK_APB2>; 466 clock-names = "ssi_clk", "pclk"; 467 resets = <&sysrst K210_RST_SPI1>; 468 reset-names = "spi"; 469 num-cs = <4>; 470 reg-io-width = <4>; 471 }; 472 473 spi3: spi@54000000 { 474 #address-cells = <1>; 475 #size-cells = <0>; 476 compatible = "snps,dwc-ssi-1.01a"; 477 reg = <0x54000000 0x200>; 478 interrupts = <4>; 479 clocks = <&sysclk K210_CLK_SPI3>, 480 <&sysclk K210_CLK_APB2>; 481 clock-names = "ssi_clk", "pclk"; 482 resets = <&sysrst K210_RST_SPI3>; 483 reset-names = "spi"; 484 485 num-cs = <4>; 486 reg-io-width = <4>; 487 }; 488 }; 489 }; 490}; 491