1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> 4 * Copyright (C) 2020 Western Digital Corporation or its affiliates. 5 */ 6#include <dt-bindings/clock/k210-clk.h> 7#include <dt-bindings/pinctrl/k210-fpioa.h> 8#include <dt-bindings/reset/k210-rst.h> 9 10/ { 11 /* 12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits 13 * wide, and the upper half of all addresses is ignored. 14 */ 15 #address-cells = <1>; 16 #size-cells = <1>; 17 compatible = "canaan,kendryte-k210"; 18 19 aliases { 20 serial0 = &uarths0; 21 serial1 = &uart1; 22 serial2 = &uart2; 23 serial3 = &uart3; 24 }; 25 26 /* 27 * The K210 has an sv39 MMU following the privileged specification v1.9. 28 * Since this is a non-ratified draft specification, the kernel does not 29 * support it and the K210 support enabled only for the !MMU case. 30 * Be consistent with this by setting the CPUs MMU type to "none". 31 */ 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 timebase-frequency = <7800000>; 36 cpu0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "canaan,k210", "riscv"; 39 reg = <0>; 40 riscv,isa = "rv64imafdc"; 41 mmu-type = "riscv,none"; 42 i-cache-block-size = <64>; 43 i-cache-size = <0x8000>; 44 d-cache-block-size = <64>; 45 d-cache-size = <0x8000>; 46 cpu0_intc: interrupt-controller { 47 #interrupt-cells = <1>; 48 interrupt-controller; 49 compatible = "riscv,cpu-intc"; 50 }; 51 }; 52 cpu1: cpu@1 { 53 device_type = "cpu"; 54 compatible = "canaan,k210", "riscv"; 55 reg = <1>; 56 riscv,isa = "rv64imafdc"; 57 mmu-type = "riscv,none"; 58 i-cache-block-size = <64>; 59 i-cache-size = <0x8000>; 60 d-cache-block-size = <64>; 61 d-cache-size = <0x8000>; 62 cpu1_intc: interrupt-controller { 63 #interrupt-cells = <1>; 64 interrupt-controller; 65 compatible = "riscv,cpu-intc"; 66 }; 67 }; 68 69 cpu-map { 70 cluster0 { 71 core0 { 72 cpu = <&cpu0>; 73 }; 74 75 core1 { 76 cpu = <&cpu1>; 77 }; 78 }; 79 }; 80 }; 81 82 sram: memory@80000000 { 83 device_type = "memory"; 84 compatible = "canaan,k210-sram"; 85 reg = <0x80000000 0x400000>, 86 <0x80400000 0x200000>, 87 <0x80600000 0x200000>; 88 reg-names = "sram0", "sram1", "aisram"; 89 clocks = <&sysclk K210_CLK_SRAM0>, 90 <&sysclk K210_CLK_SRAM1>, 91 <&sysclk K210_CLK_AI>; 92 clock-names = "sram0", "sram1", "aisram"; 93 }; 94 95 clocks { 96 in0: oscillator { 97 compatible = "fixed-clock"; 98 #clock-cells = <0>; 99 clock-frequency = <26000000>; 100 }; 101 }; 102 103 soc { 104 #address-cells = <1>; 105 #size-cells = <1>; 106 compatible = "simple-bus"; 107 ranges; 108 interrupt-parent = <&plic0>; 109 110 rom0: nvmem@1000 { 111 reg = <0x1000 0x1000>; 112 read-only; 113 }; 114 115 clint0: timer@2000000 { 116 compatible = "canaan,k210-clint", "sifive,clint0"; 117 reg = <0x2000000 0xC000>; 118 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 119 <&cpu1_intc 3>, <&cpu1_intc 7>; 120 }; 121 122 plic0: interrupt-controller@c000000 { 123 #interrupt-cells = <1>; 124 #address-cells = <0>; 125 compatible = "canaan,k210-plic", "sifive,plic-1.0.0"; 126 reg = <0xC000000 0x4000000>; 127 interrupt-controller; 128 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 129 <&cpu1_intc 11>, <&cpu1_intc 9>; 130 riscv,ndev = <65>; 131 }; 132 133 uarths0: serial@38000000 { 134 compatible = "canaan,k210-uarths", "sifive,uart0"; 135 reg = <0x38000000 0x1000>; 136 interrupts = <33>; 137 clocks = <&sysclk K210_CLK_CPU>; 138 }; 139 140 gpio0: gpio-controller@38001000 { 141 #interrupt-cells = <2>; 142 #gpio-cells = <2>; 143 compatible = "canaan,k210-gpiohs", "sifive,gpio0"; 144 reg = <0x38001000 0x1000>; 145 interrupt-controller; 146 interrupts = <34>, <35>, <36>, <37>, <38>, <39>, <40>, 147 <41>, <42>, <43>, <44>, <45>, <46>, <47>, 148 <48>, <49>, <50>, <51>, <52>, <53>, <54>, 149 <55>, <56>, <57>, <58>, <59>, <60>, <61>, 150 <62>, <63>, <64>, <65>; 151 gpio-controller; 152 ngpios = <32>; 153 }; 154 155 dmac0: dma-controller@50000000 { 156 compatible = "snps,axi-dma-1.01a"; 157 reg = <0x50000000 0x1000>; 158 interrupts = <27>, <28>, <29>, <30>, <31>, <32>; 159 #dma-cells = <1>; 160 clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; 161 clock-names = "core-clk", "cfgr-clk"; 162 resets = <&sysrst K210_RST_DMA>; 163 dma-channels = <6>; 164 snps,dma-masters = <2>; 165 snps,priority = <0 1 2 3 4 5>; 166 snps,data-width = <5>; 167 snps,block-size = <0x200000 0x200000 0x200000 168 0x200000 0x200000 0x200000>; 169 snps,axi-max-burst-len = <256>; 170 }; 171 172 apb0: bus@50200000 { 173 #address-cells = <1>; 174 #size-cells = <1>; 175 compatible = "simple-pm-bus"; 176 ranges; 177 clocks = <&sysclk K210_CLK_APB0>; 178 179 gpio1: gpio@50200000 { 180 #address-cells = <1>; 181 #size-cells = <0>; 182 compatible = "snps,dw-apb-gpio"; 183 reg = <0x50200000 0x80>; 184 clocks = <&sysclk K210_CLK_APB0>, 185 <&sysclk K210_CLK_GPIO>; 186 clock-names = "bus", "db"; 187 resets = <&sysrst K210_RST_GPIO>; 188 189 gpio1_0: gpio-port@0 { 190 #gpio-cells = <2>; 191 #interrupt-cells = <2>; 192 compatible = "snps,dw-apb-gpio-port"; 193 reg = <0>; 194 interrupt-controller; 195 interrupts = <23>; 196 gpio-controller; 197 ngpios = <8>; 198 }; 199 }; 200 201 uart1: serial@50210000 { 202 compatible = "snps,dw-apb-uart"; 203 reg = <0x50210000 0x100>; 204 interrupts = <11>; 205 clocks = <&sysclk K210_CLK_UART1>, 206 <&sysclk K210_CLK_APB0>; 207 clock-names = "baudclk", "apb_pclk"; 208 resets = <&sysrst K210_RST_UART1>; 209 reg-io-width = <4>; 210 reg-shift = <2>; 211 dcd-override; 212 dsr-override; 213 cts-override; 214 ri-override; 215 }; 216 217 uart2: serial@50220000 { 218 compatible = "snps,dw-apb-uart"; 219 reg = <0x50220000 0x100>; 220 interrupts = <12>; 221 clocks = <&sysclk K210_CLK_UART2>, 222 <&sysclk K210_CLK_APB0>; 223 clock-names = "baudclk", "apb_pclk"; 224 resets = <&sysrst K210_RST_UART2>; 225 reg-io-width = <4>; 226 reg-shift = <2>; 227 dcd-override; 228 dsr-override; 229 cts-override; 230 ri-override; 231 }; 232 233 uart3: serial@50230000 { 234 compatible = "snps,dw-apb-uart"; 235 reg = <0x50230000 0x100>; 236 interrupts = <13>; 237 clocks = <&sysclk K210_CLK_UART3>, 238 <&sysclk K210_CLK_APB0>; 239 clock-names = "baudclk", "apb_pclk"; 240 resets = <&sysrst K210_RST_UART3>; 241 reg-io-width = <4>; 242 reg-shift = <2>; 243 dcd-override; 244 dsr-override; 245 cts-override; 246 ri-override; 247 }; 248 249 spi2: spi@50240000 { 250 compatible = "canaan,k210-spi"; 251 spi-slave; 252 reg = <0x50240000 0x100>; 253 #address-cells = <0>; 254 #size-cells = <0>; 255 interrupts = <3>; 256 clocks = <&sysclk K210_CLK_SPI2>, 257 <&sysclk K210_CLK_APB0>; 258 clock-names = "ssi_clk", "pclk"; 259 resets = <&sysrst K210_RST_SPI2>; 260 spi-max-frequency = <25000000>; 261 }; 262 263 i2s0: i2s@50250000 { 264 compatible = "snps,designware-i2s"; 265 reg = <0x50250000 0x200>; 266 interrupts = <5>; 267 clocks = <&sysclk K210_CLK_I2S0>; 268 clock-names = "i2sclk"; 269 resets = <&sysrst K210_RST_I2S0>; 270 }; 271 272 i2s1: i2s@50260000 { 273 compatible = "snps,designware-i2s"; 274 reg = <0x50260000 0x200>; 275 interrupts = <6>; 276 clocks = <&sysclk K210_CLK_I2S1>; 277 clock-names = "i2sclk"; 278 resets = <&sysrst K210_RST_I2S1>; 279 }; 280 281 i2s2: i2s@50270000 { 282 compatible = "snps,designware-i2s"; 283 reg = <0x50270000 0x200>; 284 interrupts = <7>; 285 clocks = <&sysclk K210_CLK_I2S2>; 286 clock-names = "i2sclk"; 287 resets = <&sysrst K210_RST_I2S2>; 288 }; 289 290 i2c0: i2c@50280000 { 291 compatible = "snps,designware-i2c"; 292 reg = <0x50280000 0x100>; 293 interrupts = <8>; 294 clocks = <&sysclk K210_CLK_I2C0>, 295 <&sysclk K210_CLK_APB0>; 296 clock-names = "ref", "pclk"; 297 resets = <&sysrst K210_RST_I2C0>; 298 }; 299 300 i2c1: i2c@50290000 { 301 compatible = "snps,designware-i2c"; 302 reg = <0x50290000 0x100>; 303 interrupts = <9>; 304 clocks = <&sysclk K210_CLK_I2C1>, 305 <&sysclk K210_CLK_APB0>; 306 clock-names = "ref", "pclk"; 307 resets = <&sysrst K210_RST_I2C1>; 308 }; 309 310 i2c2: i2c@502a0000 { 311 compatible = "snps,designware-i2c"; 312 reg = <0x502A0000 0x100>; 313 interrupts = <10>; 314 clocks = <&sysclk K210_CLK_I2C2>, 315 <&sysclk K210_CLK_APB0>; 316 clock-names = "ref", "pclk"; 317 resets = <&sysrst K210_RST_I2C2>; 318 }; 319 320 fpioa: pinmux@502b0000 { 321 compatible = "canaan,k210-fpioa"; 322 reg = <0x502B0000 0x100>; 323 clocks = <&sysclk K210_CLK_FPIOA>, 324 <&sysclk K210_CLK_APB0>; 325 clock-names = "ref", "pclk"; 326 resets = <&sysrst K210_RST_FPIOA>; 327 canaan,k210-sysctl-power = <&sysctl 108>; 328 }; 329 330 timer0: timer@502d0000 { 331 compatible = "snps,dw-apb-timer"; 332 reg = <0x502D0000 0x100>; 333 interrupts = <14>, <15>; 334 clocks = <&sysclk K210_CLK_TIMER0>, 335 <&sysclk K210_CLK_APB0>; 336 clock-names = "timer", "pclk"; 337 resets = <&sysrst K210_RST_TIMER0>; 338 }; 339 340 timer1: timer@502e0000 { 341 compatible = "snps,dw-apb-timer"; 342 reg = <0x502E0000 0x100>; 343 interrupts = <16>, <17>; 344 clocks = <&sysclk K210_CLK_TIMER1>, 345 <&sysclk K210_CLK_APB0>; 346 clock-names = "timer", "pclk"; 347 resets = <&sysrst K210_RST_TIMER1>; 348 }; 349 350 timer2: timer@502f0000 { 351 compatible = "snps,dw-apb-timer"; 352 reg = <0x502F0000 0x100>; 353 interrupts = <18>, <19>; 354 clocks = <&sysclk K210_CLK_TIMER2>, 355 <&sysclk K210_CLK_APB0>; 356 clock-names = "timer", "pclk"; 357 resets = <&sysrst K210_RST_TIMER2>; 358 }; 359 }; 360 361 apb1: bus@50400000 { 362 #address-cells = <1>; 363 #size-cells = <1>; 364 compatible = "simple-pm-bus"; 365 ranges; 366 clocks = <&sysclk K210_CLK_APB1>; 367 368 wdt0: watchdog@50400000 { 369 compatible = "snps,dw-wdt"; 370 reg = <0x50400000 0x100>; 371 interrupts = <21>; 372 clocks = <&sysclk K210_CLK_WDT0>, 373 <&sysclk K210_CLK_APB1>; 374 clock-names = "tclk", "pclk"; 375 resets = <&sysrst K210_RST_WDT0>; 376 }; 377 378 wdt1: watchdog@50410000 { 379 compatible = "snps,dw-wdt"; 380 reg = <0x50410000 0x100>; 381 interrupts = <22>; 382 clocks = <&sysclk K210_CLK_WDT1>, 383 <&sysclk K210_CLK_APB1>; 384 clock-names = "tclk", "pclk"; 385 resets = <&sysrst K210_RST_WDT1>; 386 }; 387 388 sysctl: syscon@50440000 { 389 compatible = "canaan,k210-sysctl", 390 "syscon", "simple-mfd"; 391 reg = <0x50440000 0x100>; 392 clocks = <&sysclk K210_CLK_APB1>; 393 clock-names = "pclk"; 394 395 sysclk: clock-controller { 396 #clock-cells = <1>; 397 compatible = "canaan,k210-clk"; 398 clocks = <&in0>; 399 }; 400 401 sysrst: reset-controller { 402 compatible = "canaan,k210-rst"; 403 #reset-cells = <1>; 404 }; 405 406 reboot: syscon-reboot { 407 compatible = "syscon-reboot"; 408 regmap = <&sysctl>; 409 offset = <48>; 410 mask = <1>; 411 value = <1>; 412 }; 413 }; 414 }; 415 416 apb2: bus@52000000 { 417 #address-cells = <1>; 418 #size-cells = <1>; 419 compatible = "simple-pm-bus"; 420 ranges; 421 clocks = <&sysclk K210_CLK_APB2>; 422 423 spi0: spi@52000000 { 424 #address-cells = <1>; 425 #size-cells = <0>; 426 compatible = "canaan,k210-spi"; 427 reg = <0x52000000 0x100>; 428 interrupts = <1>; 429 clocks = <&sysclk K210_CLK_SPI0>, 430 <&sysclk K210_CLK_APB2>; 431 clock-names = "ssi_clk", "pclk"; 432 resets = <&sysrst K210_RST_SPI0>; 433 reset-names = "spi"; 434 spi-max-frequency = <25000000>; 435 num-cs = <4>; 436 reg-io-width = <4>; 437 }; 438 439 spi1: spi@53000000 { 440 #address-cells = <1>; 441 #size-cells = <0>; 442 compatible = "canaan,k210-spi"; 443 reg = <0x53000000 0x100>; 444 interrupts = <2>; 445 clocks = <&sysclk K210_CLK_SPI1>, 446 <&sysclk K210_CLK_APB2>; 447 clock-names = "ssi_clk", "pclk"; 448 resets = <&sysrst K210_RST_SPI1>; 449 reset-names = "spi"; 450 spi-max-frequency = <25000000>; 451 num-cs = <4>; 452 reg-io-width = <4>; 453 }; 454 455 spi3: spi@54000000 { 456 #address-cells = <1>; 457 #size-cells = <0>; 458 compatible = "snps,dwc-ssi-1.01a"; 459 reg = <0x54000000 0x200>; 460 interrupts = <4>; 461 clocks = <&sysclk K210_CLK_SPI3>, 462 <&sysclk K210_CLK_APB2>; 463 clock-names = "ssi_clk", "pclk"; 464 resets = <&sysrst K210_RST_SPI3>; 465 reset-names = "spi"; 466 /* Could possibly go up to 200 MHz */ 467 spi-max-frequency = <100000000>; 468 num-cs = <4>; 469 reg-io-width = <4>; 470 }; 471 }; 472 }; 473}; 474