1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> 4 * Copyright (C) 2020 Western Digital Corporation or its affiliates. 5 */ 6#include <dt-bindings/clock/k210-clk.h> 7#include <dt-bindings/pinctrl/k210-fpioa.h> 8#include <dt-bindings/reset/k210-rst.h> 9 10/ { 11 /* 12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits 13 * wide, and the upper half of all addresses is ignored. 14 */ 15 #address-cells = <1>; 16 #size-cells = <1>; 17 compatible = "canaan,kendryte-k210"; 18 19 aliases { 20 serial0 = &uarths0; 21 serial1 = &uart1; 22 serial2 = &uart2; 23 serial3 = &uart3; 24 }; 25 26 /* 27 * The K210 has an sv39 MMU following the privileged specification v1.9. 28 * Since this is a non-ratified draft specification, the kernel does not 29 * support it and the K210 support enabled only for the !MMU case. 30 * Be consistent with this by setting the CPUs MMU type to "none". 31 */ 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 timebase-frequency = <7800000>; 36 cpu0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "canaan,k210", "riscv"; 39 reg = <0>; 40 riscv,isa = "rv64imafdc"; 41 mmu-type = "riscv,none"; 42 i-cache-block-size = <64>; 43 i-cache-size = <0x8000>; 44 d-cache-block-size = <64>; 45 d-cache-size = <0x8000>; 46 cpu0_intc: interrupt-controller { 47 #interrupt-cells = <1>; 48 interrupt-controller; 49 compatible = "riscv,cpu-intc"; 50 }; 51 }; 52 cpu1: cpu@1 { 53 device_type = "cpu"; 54 compatible = "canaan,k210", "riscv"; 55 reg = <1>; 56 riscv,isa = "rv64imafdc"; 57 mmu-type = "riscv,none"; 58 i-cache-block-size = <64>; 59 i-cache-size = <0x8000>; 60 d-cache-block-size = <64>; 61 d-cache-size = <0x8000>; 62 cpu1_intc: interrupt-controller { 63 #interrupt-cells = <1>; 64 interrupt-controller; 65 compatible = "riscv,cpu-intc"; 66 }; 67 }; 68 }; 69 70 sram: memory@80000000 { 71 device_type = "memory"; 72 compatible = "canaan,k210-sram"; 73 reg = <0x80000000 0x400000>, 74 <0x80400000 0x200000>, 75 <0x80600000 0x200000>; 76 reg-names = "sram0", "sram1", "aisram"; 77 clocks = <&sysclk K210_CLK_SRAM0>, 78 <&sysclk K210_CLK_SRAM1>, 79 <&sysclk K210_CLK_AI>; 80 clock-names = "sram0", "sram1", "aisram"; 81 }; 82 83 clocks { 84 in0: oscillator { 85 compatible = "fixed-clock"; 86 #clock-cells = <0>; 87 clock-frequency = <26000000>; 88 }; 89 }; 90 91 soc { 92 #address-cells = <1>; 93 #size-cells = <1>; 94 compatible = "simple-bus"; 95 ranges; 96 interrupt-parent = <&plic0>; 97 98 rom0: nvmem@1000 { 99 reg = <0x1000 0x1000>; 100 read-only; 101 }; 102 103 clint0: timer@2000000 { 104 compatible = "canaan,k210-clint", "sifive,clint0"; 105 reg = <0x2000000 0xC000>; 106 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 107 <&cpu1_intc 3>, <&cpu1_intc 7>; 108 }; 109 110 plic0: interrupt-controller@c000000 { 111 #interrupt-cells = <1>; 112 #address-cells = <0>; 113 compatible = "canaan,k210-plic", "sifive,plic-1.0.0"; 114 reg = <0xC000000 0x4000000>; 115 interrupt-controller; 116 interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>; 117 riscv,ndev = <65>; 118 }; 119 120 uarths0: serial@38000000 { 121 compatible = "canaan,k210-uarths", "sifive,uart0"; 122 reg = <0x38000000 0x1000>; 123 interrupts = <33>; 124 clocks = <&sysclk K210_CLK_CPU>; 125 }; 126 127 gpio0: gpio-controller@38001000 { 128 #interrupt-cells = <2>; 129 #gpio-cells = <2>; 130 compatible = "canaan,k210-gpiohs", "sifive,gpio0"; 131 reg = <0x38001000 0x1000>; 132 interrupt-controller; 133 interrupts = <34>, <35>, <36>, <37>, <38>, <39>, <40>, 134 <41>, <42>, <43>, <44>, <45>, <46>, <47>, 135 <48>, <49>, <50>, <51>, <52>, <53>, <54>, 136 <55>, <56>, <57>, <58>, <59>, <60>, <61>, 137 <62>, <63>, <64>, <65>; 138 gpio-controller; 139 ngpios = <32>; 140 }; 141 142 dmac0: dma-controller@50000000 { 143 compatible = "snps,axi-dma-1.01a"; 144 reg = <0x50000000 0x1000>; 145 interrupts = <27>, <28>, <29>, <30>, <31>, <32>; 146 #dma-cells = <1>; 147 clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; 148 clock-names = "core-clk", "cfgr-clk"; 149 resets = <&sysrst K210_RST_DMA>; 150 dma-channels = <6>; 151 snps,dma-masters = <2>; 152 snps,priority = <0 1 2 3 4 5>; 153 snps,data-width = <5>; 154 snps,block-size = <0x200000 0x200000 0x200000 155 0x200000 0x200000 0x200000>; 156 snps,axi-max-burst-len = <256>; 157 }; 158 159 apb0: bus@50200000 { 160 #address-cells = <1>; 161 #size-cells = <1>; 162 compatible = "simple-pm-bus"; 163 ranges; 164 clocks = <&sysclk K210_CLK_APB0>; 165 166 gpio1: gpio@50200000 { 167 #address-cells = <1>; 168 #size-cells = <0>; 169 compatible = "snps,dw-apb-gpio"; 170 reg = <0x50200000 0x80>; 171 clocks = <&sysclk K210_CLK_APB0>, 172 <&sysclk K210_CLK_GPIO>; 173 clock-names = "bus", "db"; 174 resets = <&sysrst K210_RST_GPIO>; 175 176 gpio1_0: gpio-port@0 { 177 #gpio-cells = <2>; 178 #interrupt-cells = <2>; 179 compatible = "snps,dw-apb-gpio-port"; 180 reg = <0>; 181 interrupt-controller; 182 interrupts = <23>; 183 gpio-controller; 184 ngpios = <8>; 185 }; 186 }; 187 188 uart1: serial@50210000 { 189 compatible = "snps,dw-apb-uart"; 190 reg = <0x50210000 0x100>; 191 interrupts = <11>; 192 clocks = <&sysclk K210_CLK_UART1>, 193 <&sysclk K210_CLK_APB0>; 194 clock-names = "baudclk", "apb_pclk"; 195 resets = <&sysrst K210_RST_UART1>; 196 reg-io-width = <4>; 197 reg-shift = <2>; 198 dcd-override; 199 dsr-override; 200 cts-override; 201 ri-override; 202 }; 203 204 uart2: serial@50220000 { 205 compatible = "snps,dw-apb-uart"; 206 reg = <0x50220000 0x100>; 207 interrupts = <12>; 208 clocks = <&sysclk K210_CLK_UART2>, 209 <&sysclk K210_CLK_APB0>; 210 clock-names = "baudclk", "apb_pclk"; 211 resets = <&sysrst K210_RST_UART2>; 212 reg-io-width = <4>; 213 reg-shift = <2>; 214 dcd-override; 215 dsr-override; 216 cts-override; 217 ri-override; 218 }; 219 220 uart3: serial@50230000 { 221 compatible = "snps,dw-apb-uart"; 222 reg = <0x50230000 0x100>; 223 interrupts = <13>; 224 clocks = <&sysclk K210_CLK_UART3>, 225 <&sysclk K210_CLK_APB0>; 226 clock-names = "baudclk", "apb_pclk"; 227 resets = <&sysrst K210_RST_UART3>; 228 reg-io-width = <4>; 229 reg-shift = <2>; 230 dcd-override; 231 dsr-override; 232 cts-override; 233 ri-override; 234 }; 235 236 spi2: spi@50240000 { 237 compatible = "canaan,k210-spi"; 238 spi-slave; 239 reg = <0x50240000 0x100>; 240 #address-cells = <0>; 241 #size-cells = <0>; 242 interrupts = <3>; 243 clocks = <&sysclk K210_CLK_SPI2>, 244 <&sysclk K210_CLK_APB0>; 245 clock-names = "ssi_clk", "pclk"; 246 resets = <&sysrst K210_RST_SPI2>; 247 spi-max-frequency = <25000000>; 248 }; 249 250 i2s0: i2s@50250000 { 251 compatible = "snps,designware-i2s"; 252 reg = <0x50250000 0x200>; 253 interrupts = <5>; 254 clocks = <&sysclk K210_CLK_I2S0>; 255 clock-names = "i2sclk"; 256 resets = <&sysrst K210_RST_I2S0>; 257 }; 258 259 i2s1: i2s@50260000 { 260 compatible = "snps,designware-i2s"; 261 reg = <0x50260000 0x200>; 262 interrupts = <6>; 263 clocks = <&sysclk K210_CLK_I2S1>; 264 clock-names = "i2sclk"; 265 resets = <&sysrst K210_RST_I2S1>; 266 }; 267 268 i2s2: i2s@50270000 { 269 compatible = "snps,designware-i2s"; 270 reg = <0x50270000 0x200>; 271 interrupts = <7>; 272 clocks = <&sysclk K210_CLK_I2S2>; 273 clock-names = "i2sclk"; 274 resets = <&sysrst K210_RST_I2S2>; 275 }; 276 277 i2c0: i2c@50280000 { 278 compatible = "snps,designware-i2c"; 279 reg = <0x50280000 0x100>; 280 interrupts = <8>; 281 clocks = <&sysclk K210_CLK_I2C0>, 282 <&sysclk K210_CLK_APB0>; 283 clock-names = "ref", "pclk"; 284 resets = <&sysrst K210_RST_I2C0>; 285 }; 286 287 i2c1: i2c@50290000 { 288 compatible = "snps,designware-i2c"; 289 reg = <0x50290000 0x100>; 290 interrupts = <9>; 291 clocks = <&sysclk K210_CLK_I2C1>, 292 <&sysclk K210_CLK_APB0>; 293 clock-names = "ref", "pclk"; 294 resets = <&sysrst K210_RST_I2C1>; 295 }; 296 297 i2c2: i2c@502a0000 { 298 compatible = "snps,designware-i2c"; 299 reg = <0x502A0000 0x100>; 300 interrupts = <10>; 301 clocks = <&sysclk K210_CLK_I2C2>, 302 <&sysclk K210_CLK_APB0>; 303 clock-names = "ref", "pclk"; 304 resets = <&sysrst K210_RST_I2C2>; 305 }; 306 307 fpioa: pinmux@502b0000 { 308 compatible = "canaan,k210-fpioa"; 309 reg = <0x502B0000 0x100>; 310 clocks = <&sysclk K210_CLK_FPIOA>, 311 <&sysclk K210_CLK_APB0>; 312 clock-names = "ref", "pclk"; 313 resets = <&sysrst K210_RST_FPIOA>; 314 canaan,k210-sysctl-power = <&sysctl 108>; 315 }; 316 317 timer0: timer@502d0000 { 318 compatible = "snps,dw-apb-timer"; 319 reg = <0x502D0000 0x100>; 320 interrupts = <14>, <15>; 321 clocks = <&sysclk K210_CLK_TIMER0>, 322 <&sysclk K210_CLK_APB0>; 323 clock-names = "timer", "pclk"; 324 resets = <&sysrst K210_RST_TIMER0>; 325 }; 326 327 timer1: timer@502e0000 { 328 compatible = "snps,dw-apb-timer"; 329 reg = <0x502E0000 0x100>; 330 interrupts = <16>, <17>; 331 clocks = <&sysclk K210_CLK_TIMER1>, 332 <&sysclk K210_CLK_APB0>; 333 clock-names = "timer", "pclk"; 334 resets = <&sysrst K210_RST_TIMER1>; 335 }; 336 337 timer2: timer@502f0000 { 338 compatible = "snps,dw-apb-timer"; 339 reg = <0x502F0000 0x100>; 340 interrupts = <18>, <19>; 341 clocks = <&sysclk K210_CLK_TIMER2>, 342 <&sysclk K210_CLK_APB0>; 343 clock-names = "timer", "pclk"; 344 resets = <&sysrst K210_RST_TIMER2>; 345 }; 346 }; 347 348 apb1: bus@50400000 { 349 #address-cells = <1>; 350 #size-cells = <1>; 351 compatible = "simple-pm-bus"; 352 ranges; 353 clocks = <&sysclk K210_CLK_APB1>; 354 355 wdt0: watchdog@50400000 { 356 compatible = "snps,dw-wdt"; 357 reg = <0x50400000 0x100>; 358 interrupts = <21>; 359 clocks = <&sysclk K210_CLK_WDT0>, 360 <&sysclk K210_CLK_APB1>; 361 clock-names = "tclk", "pclk"; 362 resets = <&sysrst K210_RST_WDT0>; 363 }; 364 365 wdt1: watchdog@50410000 { 366 compatible = "snps,dw-wdt"; 367 reg = <0x50410000 0x100>; 368 interrupts = <22>; 369 clocks = <&sysclk K210_CLK_WDT1>, 370 <&sysclk K210_CLK_APB1>; 371 clock-names = "tclk", "pclk"; 372 resets = <&sysrst K210_RST_WDT1>; 373 }; 374 375 sysctl: syscon@50440000 { 376 compatible = "canaan,k210-sysctl", 377 "syscon", "simple-mfd"; 378 reg = <0x50440000 0x100>; 379 clocks = <&sysclk K210_CLK_APB1>; 380 clock-names = "pclk"; 381 382 sysclk: clock-controller { 383 #clock-cells = <1>; 384 compatible = "canaan,k210-clk"; 385 clocks = <&in0>; 386 }; 387 388 sysrst: reset-controller { 389 compatible = "canaan,k210-rst"; 390 #reset-cells = <1>; 391 }; 392 393 reboot: syscon-reboot { 394 compatible = "syscon-reboot"; 395 regmap = <&sysctl>; 396 offset = <48>; 397 mask = <1>; 398 value = <1>; 399 }; 400 }; 401 }; 402 403 apb2: bus@52000000 { 404 #address-cells = <1>; 405 #size-cells = <1>; 406 compatible = "simple-pm-bus"; 407 ranges; 408 clocks = <&sysclk K210_CLK_APB2>; 409 410 spi0: spi@52000000 { 411 #address-cells = <1>; 412 #size-cells = <0>; 413 compatible = "canaan,k210-spi"; 414 reg = <0x52000000 0x100>; 415 interrupts = <1>; 416 clocks = <&sysclk K210_CLK_SPI0>, 417 <&sysclk K210_CLK_APB2>; 418 clock-names = "ssi_clk", "pclk"; 419 resets = <&sysrst K210_RST_SPI0>; 420 reset-names = "spi"; 421 spi-max-frequency = <25000000>; 422 num-cs = <4>; 423 reg-io-width = <4>; 424 }; 425 426 spi1: spi@53000000 { 427 #address-cells = <1>; 428 #size-cells = <0>; 429 compatible = "canaan,k210-spi"; 430 reg = <0x53000000 0x100>; 431 interrupts = <2>; 432 clocks = <&sysclk K210_CLK_SPI1>, 433 <&sysclk K210_CLK_APB2>; 434 clock-names = "ssi_clk", "pclk"; 435 resets = <&sysrst K210_RST_SPI1>; 436 reset-names = "spi"; 437 spi-max-frequency = <25000000>; 438 num-cs = <4>; 439 reg-io-width = <4>; 440 }; 441 442 spi3: spi@54000000 { 443 #address-cells = <1>; 444 #size-cells = <0>; 445 compatible = "snps,dwc-ssi-1.01a"; 446 reg = <0x54000000 0x200>; 447 interrupts = <4>; 448 clocks = <&sysclk K210_CLK_SPI3>, 449 <&sysclk K210_CLK_APB2>; 450 clock-names = "ssi_clk", "pclk"; 451 resets = <&sysrst K210_RST_SPI3>; 452 reset-names = "spi"; 453 /* Could possibly go up to 200 MHz */ 454 spi-max-frequency = <100000000>; 455 num-cs = <4>; 456 reg-io-width = <4>; 457 }; 458 }; 459 }; 460}; 461