108734e05SDamien Le Moal// SPDX-License-Identifier: GPL-2.0+ 208734e05SDamien Le Moal/* 367d96729SDamien Le Moal * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> 408734e05SDamien Le Moal * Copyright (C) 2020 Western Digital Corporation or its affiliates. 508734e05SDamien Le Moal */ 608734e05SDamien Le Moal#include <dt-bindings/clock/k210-clk.h> 767d96729SDamien Le Moal#include <dt-bindings/pinctrl/k210-fpioa.h> 867d96729SDamien Le Moal#include <dt-bindings/reset/k210-rst.h> 908734e05SDamien Le Moal 1008734e05SDamien Le Moal/ { 1108734e05SDamien Le Moal /* 1208734e05SDamien Le Moal * Although the K210 is a 64-bit CPU, the address bus is only 32-bits 1308734e05SDamien Le Moal * wide, and the upper half of all addresses is ignored. 1408734e05SDamien Le Moal */ 1508734e05SDamien Le Moal #address-cells = <1>; 1608734e05SDamien Le Moal #size-cells = <1>; 1767d96729SDamien Le Moal compatible = "canaan,kendryte-k210"; 1808734e05SDamien Le Moal 1908734e05SDamien Le Moal aliases { 2008734e05SDamien Le Moal serial0 = &uarths0; 2167d96729SDamien Le Moal serial1 = &uart1; 2267d96729SDamien Le Moal serial2 = &uart2; 2367d96729SDamien Le Moal serial3 = &uart3; 2408734e05SDamien Le Moal }; 2508734e05SDamien Le Moal 2608734e05SDamien Le Moal /* 2767d96729SDamien Le Moal * The K210 has an sv39 MMU following the privileged specification v1.9. 2808734e05SDamien Le Moal * Since this is a non-ratified draft specification, the kernel does not 2908734e05SDamien Le Moal * support it and the K210 support enabled only for the !MMU case. 3008734e05SDamien Le Moal * Be consistent with this by setting the CPUs MMU type to "none". 3108734e05SDamien Le Moal */ 3208734e05SDamien Le Moal cpus { 3308734e05SDamien Le Moal #address-cells = <1>; 3408734e05SDamien Le Moal #size-cells = <0>; 3508734e05SDamien Le Moal timebase-frequency = <7800000>; 3608734e05SDamien Le Moal cpu0: cpu@0 { 3708734e05SDamien Le Moal device_type = "cpu"; 3867d96729SDamien Le Moal compatible = "canaan,k210", "riscv"; 3908734e05SDamien Le Moal reg = <0>; 4008734e05SDamien Le Moal riscv,isa = "rv64imafdc"; 4167d96729SDamien Le Moal mmu-type = "riscv,none"; 4208734e05SDamien Le Moal i-cache-block-size = <64>; 4367d96729SDamien Le Moal i-cache-size = <0x8000>; 4408734e05SDamien Le Moal d-cache-block-size = <64>; 4567d96729SDamien Le Moal d-cache-size = <0x8000>; 4608734e05SDamien Le Moal cpu0_intc: interrupt-controller { 4708734e05SDamien Le Moal #interrupt-cells = <1>; 4808734e05SDamien Le Moal interrupt-controller; 4908734e05SDamien Le Moal compatible = "riscv,cpu-intc"; 5008734e05SDamien Le Moal }; 5108734e05SDamien Le Moal }; 5208734e05SDamien Le Moal cpu1: cpu@1 { 5308734e05SDamien Le Moal device_type = "cpu"; 5467d96729SDamien Le Moal compatible = "canaan,k210", "riscv"; 5508734e05SDamien Le Moal reg = <1>; 5608734e05SDamien Le Moal riscv,isa = "rv64imafdc"; 5767d96729SDamien Le Moal mmu-type = "riscv,none"; 5808734e05SDamien Le Moal i-cache-block-size = <64>; 5967d96729SDamien Le Moal i-cache-size = <0x8000>; 6008734e05SDamien Le Moal d-cache-block-size = <64>; 6167d96729SDamien Le Moal d-cache-size = <0x8000>; 6208734e05SDamien Le Moal cpu1_intc: interrupt-controller { 6308734e05SDamien Le Moal #interrupt-cells = <1>; 6408734e05SDamien Le Moal interrupt-controller; 6508734e05SDamien Le Moal compatible = "riscv,cpu-intc"; 6608734e05SDamien Le Moal }; 6708734e05SDamien Le Moal }; 6808734e05SDamien Le Moal }; 6908734e05SDamien Le Moal 7008734e05SDamien Le Moal sram: memory@80000000 { 7108734e05SDamien Le Moal device_type = "memory"; 72465c1274SConor Dooley reg = <0x80000000 0x400000>, /* sram0 4 MiB */ 73465c1274SConor Dooley <0x80400000 0x200000>, /* sram1 2 MiB */ 74465c1274SConor Dooley <0x80600000 0x200000>; /* aisram 2 MiB */ 75465c1274SConor Dooley }; 76465c1274SConor Dooley 77465c1274SConor Dooley sram_controller: memory-controller { 7867d96729SDamien Le Moal compatible = "canaan,k210-sram"; 7967d96729SDamien Le Moal clocks = <&sysclk K210_CLK_SRAM0>, 8067d96729SDamien Le Moal <&sysclk K210_CLK_SRAM1>, 8167d96729SDamien Le Moal <&sysclk K210_CLK_AI>; 8267d96729SDamien Le Moal clock-names = "sram0", "sram1", "aisram"; 8308734e05SDamien Le Moal }; 8408734e05SDamien Le Moal 8508734e05SDamien Le Moal clocks { 8608734e05SDamien Le Moal in0: oscillator { 8708734e05SDamien Le Moal compatible = "fixed-clock"; 8808734e05SDamien Le Moal #clock-cells = <0>; 8908734e05SDamien Le Moal clock-frequency = <26000000>; 9008734e05SDamien Le Moal }; 9108734e05SDamien Le Moal }; 9208734e05SDamien Le Moal 9308734e05SDamien Le Moal soc { 9408734e05SDamien Le Moal #address-cells = <1>; 9508734e05SDamien Le Moal #size-cells = <1>; 9667d96729SDamien Le Moal compatible = "simple-bus"; 9708734e05SDamien Le Moal ranges; 9808734e05SDamien Le Moal interrupt-parent = <&plic0>; 9908734e05SDamien Le Moal 10067d96729SDamien Le Moal rom0: nvmem@1000 { 10167d96729SDamien Le Moal reg = <0x1000 0x1000>; 10267d96729SDamien Le Moal read-only; 10308734e05SDamien Le Moal }; 10408734e05SDamien Le Moal 10567d96729SDamien Le Moal clint0: timer@2000000 { 10667d96729SDamien Le Moal compatible = "canaan,k210-clint", "sifive,clint0"; 10708734e05SDamien Le Moal reg = <0x2000000 0xC000>; 10875c0dc04SGeert Uytterhoeven interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 10975c0dc04SGeert Uytterhoeven <&cpu1_intc 3>, <&cpu1_intc 7>; 11008734e05SDamien Le Moal }; 11108734e05SDamien Le Moal 11208734e05SDamien Le Moal plic0: interrupt-controller@c000000 { 11308734e05SDamien Le Moal #interrupt-cells = <1>; 11467d96729SDamien Le Moal #address-cells = <0>; 11567d96729SDamien Le Moal compatible = "canaan,k210-plic", "sifive,plic-1.0.0"; 11608734e05SDamien Le Moal reg = <0xC000000 0x4000000>; 11767d96729SDamien Le Moal interrupt-controller; 11874583f1bSNiklas Cassel interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 11974583f1bSNiklas Cassel <&cpu1_intc 11>, <&cpu1_intc 9>; 12008734e05SDamien Le Moal riscv,ndev = <65>; 12108734e05SDamien Le Moal }; 12208734e05SDamien Le Moal 12308734e05SDamien Le Moal uarths0: serial@38000000 { 12467d96729SDamien Le Moal compatible = "canaan,k210-uarths", "sifive,uart0"; 12508734e05SDamien Le Moal reg = <0x38000000 0x1000>; 12608734e05SDamien Le Moal interrupts = <33>; 12767d96729SDamien Le Moal clocks = <&sysclk K210_CLK_CPU>; 12867d96729SDamien Le Moal }; 12967d96729SDamien Le Moal 13067d96729SDamien Le Moal gpio0: gpio-controller@38001000 { 13167d96729SDamien Le Moal #interrupt-cells = <2>; 13267d96729SDamien Le Moal #gpio-cells = <2>; 13367d96729SDamien Le Moal compatible = "canaan,k210-gpiohs", "sifive,gpio0"; 13467d96729SDamien Le Moal reg = <0x38001000 0x1000>; 13567d96729SDamien Le Moal interrupt-controller; 13675c0dc04SGeert Uytterhoeven interrupts = <34>, <35>, <36>, <37>, <38>, <39>, <40>, 13775c0dc04SGeert Uytterhoeven <41>, <42>, <43>, <44>, <45>, <46>, <47>, 13875c0dc04SGeert Uytterhoeven <48>, <49>, <50>, <51>, <52>, <53>, <54>, 13975c0dc04SGeert Uytterhoeven <55>, <56>, <57>, <58>, <59>, <60>, <61>, 14075c0dc04SGeert Uytterhoeven <62>, <63>, <64>, <65>; 14167d96729SDamien Le Moal gpio-controller; 14267d96729SDamien Le Moal ngpios = <32>; 14367d96729SDamien Le Moal }; 14467d96729SDamien Le Moal 14567d96729SDamien Le Moal dmac0: dma-controller@50000000 { 14667d96729SDamien Le Moal compatible = "snps,axi-dma-1.01a"; 14767d96729SDamien Le Moal reg = <0x50000000 0x1000>; 14875c0dc04SGeert Uytterhoeven interrupts = <27>, <28>, <29>, <30>, <31>, <32>; 14967d96729SDamien Le Moal #dma-cells = <1>; 15067d96729SDamien Le Moal clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; 15167d96729SDamien Le Moal clock-names = "core-clk", "cfgr-clk"; 15267d96729SDamien Le Moal resets = <&sysrst K210_RST_DMA>; 15367d96729SDamien Le Moal dma-channels = <6>; 15467d96729SDamien Le Moal snps,dma-masters = <2>; 15567d96729SDamien Le Moal snps,priority = <0 1 2 3 4 5>; 15667d96729SDamien Le Moal snps,data-width = <5>; 15767d96729SDamien Le Moal snps,block-size = <0x200000 0x200000 0x200000 15867d96729SDamien Le Moal 0x200000 0x200000 0x200000>; 15967d96729SDamien Le Moal snps,axi-max-burst-len = <256>; 16067d96729SDamien Le Moal }; 16167d96729SDamien Le Moal 16267d96729SDamien Le Moal apb0: bus@50200000 { 16367d96729SDamien Le Moal #address-cells = <1>; 16467d96729SDamien Le Moal #size-cells = <1>; 16567d96729SDamien Le Moal compatible = "simple-pm-bus"; 166*e19f975aSConor Dooley ranges = <0x50200000 0x50200000 0x200000>; 16767d96729SDamien Le Moal clocks = <&sysclk K210_CLK_APB0>; 16867d96729SDamien Le Moal 16967d96729SDamien Le Moal gpio1: gpio@50200000 { 17067d96729SDamien Le Moal #address-cells = <1>; 17167d96729SDamien Le Moal #size-cells = <0>; 17267d96729SDamien Le Moal compatible = "snps,dw-apb-gpio"; 17367d96729SDamien Le Moal reg = <0x50200000 0x80>; 17467d96729SDamien Le Moal clocks = <&sysclk K210_CLK_APB0>, 17567d96729SDamien Le Moal <&sysclk K210_CLK_GPIO>; 17667d96729SDamien Le Moal clock-names = "bus", "db"; 17767d96729SDamien Le Moal resets = <&sysrst K210_RST_GPIO>; 17867d96729SDamien Le Moal 17967d96729SDamien Le Moal gpio1_0: gpio-port@0 { 18067d96729SDamien Le Moal #gpio-cells = <2>; 18167d96729SDamien Le Moal #interrupt-cells = <2>; 18267d96729SDamien Le Moal compatible = "snps,dw-apb-gpio-port"; 18367d96729SDamien Le Moal reg = <0>; 18467d96729SDamien Le Moal interrupt-controller; 18567d96729SDamien Le Moal interrupts = <23>; 18667d96729SDamien Le Moal gpio-controller; 18767d96729SDamien Le Moal ngpios = <8>; 18867d96729SDamien Le Moal }; 18967d96729SDamien Le Moal }; 19067d96729SDamien Le Moal 19167d96729SDamien Le Moal uart1: serial@50210000 { 19267d96729SDamien Le Moal compatible = "snps,dw-apb-uart"; 19367d96729SDamien Le Moal reg = <0x50210000 0x100>; 19467d96729SDamien Le Moal interrupts = <11>; 19567d96729SDamien Le Moal clocks = <&sysclk K210_CLK_UART1>, 19667d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 19767d96729SDamien Le Moal clock-names = "baudclk", "apb_pclk"; 19867d96729SDamien Le Moal resets = <&sysrst K210_RST_UART1>; 19967d96729SDamien Le Moal reg-io-width = <4>; 20067d96729SDamien Le Moal reg-shift = <2>; 20167d96729SDamien Le Moal dcd-override; 20267d96729SDamien Le Moal dsr-override; 20367d96729SDamien Le Moal cts-override; 20467d96729SDamien Le Moal ri-override; 20567d96729SDamien Le Moal }; 20667d96729SDamien Le Moal 20767d96729SDamien Le Moal uart2: serial@50220000 { 20867d96729SDamien Le Moal compatible = "snps,dw-apb-uart"; 20967d96729SDamien Le Moal reg = <0x50220000 0x100>; 21067d96729SDamien Le Moal interrupts = <12>; 21167d96729SDamien Le Moal clocks = <&sysclk K210_CLK_UART2>, 21267d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 21367d96729SDamien Le Moal clock-names = "baudclk", "apb_pclk"; 21467d96729SDamien Le Moal resets = <&sysrst K210_RST_UART2>; 21567d96729SDamien Le Moal reg-io-width = <4>; 21667d96729SDamien Le Moal reg-shift = <2>; 21767d96729SDamien Le Moal dcd-override; 21867d96729SDamien Le Moal dsr-override; 21967d96729SDamien Le Moal cts-override; 22067d96729SDamien Le Moal ri-override; 22167d96729SDamien Le Moal }; 22267d96729SDamien Le Moal 22367d96729SDamien Le Moal uart3: serial@50230000 { 22467d96729SDamien Le Moal compatible = "snps,dw-apb-uart"; 22567d96729SDamien Le Moal reg = <0x50230000 0x100>; 22667d96729SDamien Le Moal interrupts = <13>; 22767d96729SDamien Le Moal clocks = <&sysclk K210_CLK_UART3>, 22867d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 22967d96729SDamien Le Moal clock-names = "baudclk", "apb_pclk"; 23067d96729SDamien Le Moal resets = <&sysrst K210_RST_UART3>; 23167d96729SDamien Le Moal reg-io-width = <4>; 23267d96729SDamien Le Moal reg-shift = <2>; 23367d96729SDamien Le Moal dcd-override; 23467d96729SDamien Le Moal dsr-override; 23567d96729SDamien Le Moal cts-override; 23667d96729SDamien Le Moal ri-override; 23767d96729SDamien Le Moal }; 23867d96729SDamien Le Moal 23967d96729SDamien Le Moal spi2: spi@50240000 { 24067d96729SDamien Le Moal compatible = "canaan,k210-spi"; 24167d96729SDamien Le Moal spi-slave; 24267d96729SDamien Le Moal reg = <0x50240000 0x100>; 24367d96729SDamien Le Moal #address-cells = <0>; 24467d96729SDamien Le Moal #size-cells = <0>; 24567d96729SDamien Le Moal interrupts = <3>; 24667d96729SDamien Le Moal clocks = <&sysclk K210_CLK_SPI2>, 24767d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 24867d96729SDamien Le Moal clock-names = "ssi_clk", "pclk"; 24967d96729SDamien Le Moal resets = <&sysrst K210_RST_SPI2>; 25067d96729SDamien Le Moal spi-max-frequency = <25000000>; 25167d96729SDamien Le Moal }; 25267d96729SDamien Le Moal 25367d96729SDamien Le Moal i2s0: i2s@50250000 { 2549bd61febSConor Dooley compatible = "canaan,k210-i2s", "snps,designware-i2s"; 25567d96729SDamien Le Moal reg = <0x50250000 0x200>; 25667d96729SDamien Le Moal interrupts = <5>; 25767d96729SDamien Le Moal clocks = <&sysclk K210_CLK_I2S0>; 25867d96729SDamien Le Moal clock-names = "i2sclk"; 25967d96729SDamien Le Moal resets = <&sysrst K210_RST_I2S0>; 26067d96729SDamien Le Moal }; 26167d96729SDamien Le Moal 26267d96729SDamien Le Moal i2s1: i2s@50260000 { 2639bd61febSConor Dooley compatible = "canaan,k210-i2s", "snps,designware-i2s"; 26467d96729SDamien Le Moal reg = <0x50260000 0x200>; 26567d96729SDamien Le Moal interrupts = <6>; 26667d96729SDamien Le Moal clocks = <&sysclk K210_CLK_I2S1>; 26767d96729SDamien Le Moal clock-names = "i2sclk"; 26867d96729SDamien Le Moal resets = <&sysrst K210_RST_I2S1>; 26967d96729SDamien Le Moal }; 27067d96729SDamien Le Moal 27167d96729SDamien Le Moal i2s2: i2s@50270000 { 2729bd61febSConor Dooley compatible = "canaan,k210-i2s", "snps,designware-i2s"; 27367d96729SDamien Le Moal reg = <0x50270000 0x200>; 27467d96729SDamien Le Moal interrupts = <7>; 27567d96729SDamien Le Moal clocks = <&sysclk K210_CLK_I2S2>; 27667d96729SDamien Le Moal clock-names = "i2sclk"; 27767d96729SDamien Le Moal resets = <&sysrst K210_RST_I2S2>; 27867d96729SDamien Le Moal }; 27967d96729SDamien Le Moal 28067d96729SDamien Le Moal i2c0: i2c@50280000 { 28167d96729SDamien Le Moal compatible = "snps,designware-i2c"; 28267d96729SDamien Le Moal reg = <0x50280000 0x100>; 28367d96729SDamien Le Moal interrupts = <8>; 28467d96729SDamien Le Moal clocks = <&sysclk K210_CLK_I2C0>, 28567d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 28667d96729SDamien Le Moal clock-names = "ref", "pclk"; 28767d96729SDamien Le Moal resets = <&sysrst K210_RST_I2C0>; 28867d96729SDamien Le Moal }; 28967d96729SDamien Le Moal 29067d96729SDamien Le Moal i2c1: i2c@50290000 { 29167d96729SDamien Le Moal compatible = "snps,designware-i2c"; 29267d96729SDamien Le Moal reg = <0x50290000 0x100>; 29367d96729SDamien Le Moal interrupts = <9>; 29467d96729SDamien Le Moal clocks = <&sysclk K210_CLK_I2C1>, 29567d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 29667d96729SDamien Le Moal clock-names = "ref", "pclk"; 29767d96729SDamien Le Moal resets = <&sysrst K210_RST_I2C1>; 29867d96729SDamien Le Moal }; 29967d96729SDamien Le Moal 30067d96729SDamien Le Moal i2c2: i2c@502a0000 { 30167d96729SDamien Le Moal compatible = "snps,designware-i2c"; 30267d96729SDamien Le Moal reg = <0x502A0000 0x100>; 30367d96729SDamien Le Moal interrupts = <10>; 30467d96729SDamien Le Moal clocks = <&sysclk K210_CLK_I2C2>, 30567d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 30667d96729SDamien Le Moal clock-names = "ref", "pclk"; 30767d96729SDamien Le Moal resets = <&sysrst K210_RST_I2C2>; 30867d96729SDamien Le Moal }; 30967d96729SDamien Le Moal 31067d96729SDamien Le Moal fpioa: pinmux@502b0000 { 31167d96729SDamien Le Moal compatible = "canaan,k210-fpioa"; 31267d96729SDamien Le Moal reg = <0x502B0000 0x100>; 31367d96729SDamien Le Moal clocks = <&sysclk K210_CLK_FPIOA>, 31467d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 31567d96729SDamien Le Moal clock-names = "ref", "pclk"; 31667d96729SDamien Le Moal resets = <&sysrst K210_RST_FPIOA>; 31767d96729SDamien Le Moal canaan,k210-sysctl-power = <&sysctl 108>; 31867d96729SDamien Le Moal }; 31967d96729SDamien Le Moal 32067d96729SDamien Le Moal timer0: timer@502d0000 { 32167d96729SDamien Le Moal compatible = "snps,dw-apb-timer"; 3223f64510eSConor Dooley reg = <0x502D0000 0x14>; 3233f64510eSConor Dooley interrupts = <14>; 32467d96729SDamien Le Moal clocks = <&sysclk K210_CLK_TIMER0>, 32567d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 32667d96729SDamien Le Moal clock-names = "timer", "pclk"; 32767d96729SDamien Le Moal resets = <&sysrst K210_RST_TIMER0>; 32867d96729SDamien Le Moal }; 32967d96729SDamien Le Moal 3303f64510eSConor Dooley timer1: timer@502d0014 { 33167d96729SDamien Le Moal compatible = "snps,dw-apb-timer"; 3323f64510eSConor Dooley reg = <0x502D0014 0x14>; 3333f64510eSConor Dooley interrupts = <15>; 3343f64510eSConor Dooley clocks = <&sysclk K210_CLK_TIMER0>, 3353f64510eSConor Dooley <&sysclk K210_CLK_APB0>; 3363f64510eSConor Dooley clock-names = "timer", "pclk"; 3373f64510eSConor Dooley resets = <&sysrst K210_RST_TIMER0>; 3383f64510eSConor Dooley }; 3393f64510eSConor Dooley 3403f64510eSConor Dooley timer2: timer@502e0000 { 3413f64510eSConor Dooley compatible = "snps,dw-apb-timer"; 3423f64510eSConor Dooley reg = <0x502E0000 0x14>; 3433f64510eSConor Dooley interrupts = <16>; 34467d96729SDamien Le Moal clocks = <&sysclk K210_CLK_TIMER1>, 34567d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 34667d96729SDamien Le Moal clock-names = "timer", "pclk"; 34767d96729SDamien Le Moal resets = <&sysrst K210_RST_TIMER1>; 34867d96729SDamien Le Moal }; 34967d96729SDamien Le Moal 3503f64510eSConor Dooley timer3: timer@502e0014 { 35167d96729SDamien Le Moal compatible = "snps,dw-apb-timer"; 3523f64510eSConor Dooley reg = <0x502E0014 0x114>; 3533f64510eSConor Dooley interrupts = <17>; 3543f64510eSConor Dooley clocks = <&sysclk K210_CLK_TIMER1>, 3553f64510eSConor Dooley <&sysclk K210_CLK_APB0>; 3563f64510eSConor Dooley clock-names = "timer", "pclk"; 3573f64510eSConor Dooley resets = <&sysrst K210_RST_TIMER1>; 3583f64510eSConor Dooley }; 3593f64510eSConor Dooley 3603f64510eSConor Dooley timer4: timer@502f0000 { 3613f64510eSConor Dooley compatible = "snps,dw-apb-timer"; 3623f64510eSConor Dooley reg = <0x502F0000 0x14>; 3633f64510eSConor Dooley interrupts = <18>; 3643f64510eSConor Dooley clocks = <&sysclk K210_CLK_TIMER2>, 3653f64510eSConor Dooley <&sysclk K210_CLK_APB0>; 3663f64510eSConor Dooley clock-names = "timer", "pclk"; 3673f64510eSConor Dooley resets = <&sysrst K210_RST_TIMER2>; 3683f64510eSConor Dooley }; 3693f64510eSConor Dooley 3703f64510eSConor Dooley timer5: timer@502f0014 { 3713f64510eSConor Dooley compatible = "snps,dw-apb-timer"; 3723f64510eSConor Dooley reg = <0x502F0014 0x14>; 3733f64510eSConor Dooley interrupts = <19>; 37467d96729SDamien Le Moal clocks = <&sysclk K210_CLK_TIMER2>, 37567d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 37667d96729SDamien Le Moal clock-names = "timer", "pclk"; 37767d96729SDamien Le Moal resets = <&sysrst K210_RST_TIMER2>; 37867d96729SDamien Le Moal }; 37967d96729SDamien Le Moal }; 38067d96729SDamien Le Moal 38167d96729SDamien Le Moal apb1: bus@50400000 { 38267d96729SDamien Le Moal #address-cells = <1>; 38367d96729SDamien Le Moal #size-cells = <1>; 38467d96729SDamien Le Moal compatible = "simple-pm-bus"; 385*e19f975aSConor Dooley ranges = <0x50400000 0x50400000 0x40100>; 38667d96729SDamien Le Moal clocks = <&sysclk K210_CLK_APB1>; 38767d96729SDamien Le Moal 38867d96729SDamien Le Moal wdt0: watchdog@50400000 { 38967d96729SDamien Le Moal compatible = "snps,dw-wdt"; 39067d96729SDamien Le Moal reg = <0x50400000 0x100>; 39167d96729SDamien Le Moal interrupts = <21>; 39267d96729SDamien Le Moal clocks = <&sysclk K210_CLK_WDT0>, 39367d96729SDamien Le Moal <&sysclk K210_CLK_APB1>; 39467d96729SDamien Le Moal clock-names = "tclk", "pclk"; 39567d96729SDamien Le Moal resets = <&sysrst K210_RST_WDT0>; 39667d96729SDamien Le Moal }; 39767d96729SDamien Le Moal 39867d96729SDamien Le Moal wdt1: watchdog@50410000 { 39967d96729SDamien Le Moal compatible = "snps,dw-wdt"; 40067d96729SDamien Le Moal reg = <0x50410000 0x100>; 40167d96729SDamien Le Moal interrupts = <22>; 40267d96729SDamien Le Moal clocks = <&sysclk K210_CLK_WDT1>, 40367d96729SDamien Le Moal <&sysclk K210_CLK_APB1>; 40467d96729SDamien Le Moal clock-names = "tclk", "pclk"; 40567d96729SDamien Le Moal resets = <&sysrst K210_RST_WDT1>; 40667d96729SDamien Le Moal }; 40767d96729SDamien Le Moal 40867d96729SDamien Le Moal sysctl: syscon@50440000 { 40967d96729SDamien Le Moal compatible = "canaan,k210-sysctl", 41067d96729SDamien Le Moal "syscon", "simple-mfd"; 41167d96729SDamien Le Moal reg = <0x50440000 0x100>; 41267d96729SDamien Le Moal clocks = <&sysclk K210_CLK_APB1>; 41367d96729SDamien Le Moal clock-names = "pclk"; 41467d96729SDamien Le Moal 41567d96729SDamien Le Moal sysclk: clock-controller { 41667d96729SDamien Le Moal #clock-cells = <1>; 41767d96729SDamien Le Moal compatible = "canaan,k210-clk"; 41867d96729SDamien Le Moal clocks = <&in0>; 41967d96729SDamien Le Moal }; 42067d96729SDamien Le Moal 42167d96729SDamien Le Moal sysrst: reset-controller { 42267d96729SDamien Le Moal compatible = "canaan,k210-rst"; 42367d96729SDamien Le Moal #reset-cells = <1>; 42467d96729SDamien Le Moal }; 42567d96729SDamien Le Moal 42667d96729SDamien Le Moal reboot: syscon-reboot { 42767d96729SDamien Le Moal compatible = "syscon-reboot"; 42867d96729SDamien Le Moal regmap = <&sysctl>; 42967d96729SDamien Le Moal offset = <48>; 43067d96729SDamien Le Moal mask = <1>; 43167d96729SDamien Le Moal value = <1>; 43267d96729SDamien Le Moal }; 43367d96729SDamien Le Moal }; 43467d96729SDamien Le Moal }; 43567d96729SDamien Le Moal 43667d96729SDamien Le Moal apb2: bus@52000000 { 43767d96729SDamien Le Moal #address-cells = <1>; 43867d96729SDamien Le Moal #size-cells = <1>; 43967d96729SDamien Le Moal compatible = "simple-pm-bus"; 440*e19f975aSConor Dooley ranges = <0x52000000 0x52000000 0x2000200>; 44167d96729SDamien Le Moal clocks = <&sysclk K210_CLK_APB2>; 44267d96729SDamien Le Moal 44367d96729SDamien Le Moal spi0: spi@52000000 { 44467d96729SDamien Le Moal #address-cells = <1>; 44567d96729SDamien Le Moal #size-cells = <0>; 44667d96729SDamien Le Moal compatible = "canaan,k210-spi"; 44767d96729SDamien Le Moal reg = <0x52000000 0x100>; 44867d96729SDamien Le Moal interrupts = <1>; 44967d96729SDamien Le Moal clocks = <&sysclk K210_CLK_SPI0>, 45067d96729SDamien Le Moal <&sysclk K210_CLK_APB2>; 45167d96729SDamien Le Moal clock-names = "ssi_clk", "pclk"; 45267d96729SDamien Le Moal resets = <&sysrst K210_RST_SPI0>; 45367d96729SDamien Le Moal reset-names = "spi"; 45467d96729SDamien Le Moal num-cs = <4>; 45567d96729SDamien Le Moal reg-io-width = <4>; 45667d96729SDamien Le Moal }; 45767d96729SDamien Le Moal 45867d96729SDamien Le Moal spi1: spi@53000000 { 45967d96729SDamien Le Moal #address-cells = <1>; 46067d96729SDamien Le Moal #size-cells = <0>; 46167d96729SDamien Le Moal compatible = "canaan,k210-spi"; 46267d96729SDamien Le Moal reg = <0x53000000 0x100>; 46367d96729SDamien Le Moal interrupts = <2>; 46467d96729SDamien Le Moal clocks = <&sysclk K210_CLK_SPI1>, 46567d96729SDamien Le Moal <&sysclk K210_CLK_APB2>; 46667d96729SDamien Le Moal clock-names = "ssi_clk", "pclk"; 46767d96729SDamien Le Moal resets = <&sysrst K210_RST_SPI1>; 46867d96729SDamien Le Moal reset-names = "spi"; 46967d96729SDamien Le Moal num-cs = <4>; 47067d96729SDamien Le Moal reg-io-width = <4>; 47167d96729SDamien Le Moal }; 47267d96729SDamien Le Moal 47367d96729SDamien Le Moal spi3: spi@54000000 { 47467d96729SDamien Le Moal #address-cells = <1>; 47567d96729SDamien Le Moal #size-cells = <0>; 47667d96729SDamien Le Moal compatible = "snps,dwc-ssi-1.01a"; 47767d96729SDamien Le Moal reg = <0x54000000 0x200>; 47867d96729SDamien Le Moal interrupts = <4>; 47967d96729SDamien Le Moal clocks = <&sysclk K210_CLK_SPI3>, 48067d96729SDamien Le Moal <&sysclk K210_CLK_APB2>; 48167d96729SDamien Le Moal clock-names = "ssi_clk", "pclk"; 48267d96729SDamien Le Moal resets = <&sysrst K210_RST_SPI3>; 48367d96729SDamien Le Moal reset-names = "spi"; 484719a85a2SConor Dooley 48567d96729SDamien Le Moal num-cs = <4>; 48667d96729SDamien Le Moal reg-io-width = <4>; 48767d96729SDamien Le Moal }; 48808734e05SDamien Le Moal }; 48908734e05SDamien Le Moal }; 49008734e05SDamien Le Moal}; 491