108734e05SDamien Le Moal// SPDX-License-Identifier: GPL-2.0+ 208734e05SDamien Le Moal/* 367d96729SDamien Le Moal * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> 408734e05SDamien Le Moal * Copyright (C) 2020 Western Digital Corporation or its affiliates. 508734e05SDamien Le Moal */ 608734e05SDamien Le Moal#include <dt-bindings/clock/k210-clk.h> 767d96729SDamien Le Moal#include <dt-bindings/pinctrl/k210-fpioa.h> 867d96729SDamien Le Moal#include <dt-bindings/reset/k210-rst.h> 908734e05SDamien Le Moal 1008734e05SDamien Le Moal/ { 1108734e05SDamien Le Moal /* 1208734e05SDamien Le Moal * Although the K210 is a 64-bit CPU, the address bus is only 32-bits 1308734e05SDamien Le Moal * wide, and the upper half of all addresses is ignored. 1408734e05SDamien Le Moal */ 1508734e05SDamien Le Moal #address-cells = <1>; 1608734e05SDamien Le Moal #size-cells = <1>; 1767d96729SDamien Le Moal compatible = "canaan,kendryte-k210"; 1808734e05SDamien Le Moal 1908734e05SDamien Le Moal aliases { 2008734e05SDamien Le Moal serial0 = &uarths0; 2167d96729SDamien Le Moal serial1 = &uart1; 2267d96729SDamien Le Moal serial2 = &uart2; 2367d96729SDamien Le Moal serial3 = &uart3; 2408734e05SDamien Le Moal }; 2508734e05SDamien Le Moal 2608734e05SDamien Le Moal /* 2767d96729SDamien Le Moal * The K210 has an sv39 MMU following the privileged specification v1.9. 2808734e05SDamien Le Moal * Since this is a non-ratified draft specification, the kernel does not 2908734e05SDamien Le Moal * support it and the K210 support enabled only for the !MMU case. 3008734e05SDamien Le Moal * Be consistent with this by setting the CPUs MMU type to "none". 3108734e05SDamien Le Moal */ 3208734e05SDamien Le Moal cpus { 3308734e05SDamien Le Moal #address-cells = <1>; 3408734e05SDamien Le Moal #size-cells = <0>; 3508734e05SDamien Le Moal timebase-frequency = <7800000>; 3608734e05SDamien Le Moal cpu0: cpu@0 { 3708734e05SDamien Le Moal device_type = "cpu"; 3867d96729SDamien Le Moal compatible = "canaan,k210", "riscv"; 3908734e05SDamien Le Moal reg = <0>; 4008734e05SDamien Le Moal riscv,isa = "rv64imafdc"; 4167d96729SDamien Le Moal mmu-type = "riscv,none"; 4208734e05SDamien Le Moal i-cache-block-size = <64>; 4367d96729SDamien Le Moal i-cache-size = <0x8000>; 4408734e05SDamien Le Moal d-cache-block-size = <64>; 4567d96729SDamien Le Moal d-cache-size = <0x8000>; 4608734e05SDamien Le Moal cpu0_intc: interrupt-controller { 4708734e05SDamien Le Moal #interrupt-cells = <1>; 4808734e05SDamien Le Moal interrupt-controller; 4908734e05SDamien Le Moal compatible = "riscv,cpu-intc"; 5008734e05SDamien Le Moal }; 5108734e05SDamien Le Moal }; 5208734e05SDamien Le Moal cpu1: cpu@1 { 5308734e05SDamien Le Moal device_type = "cpu"; 5467d96729SDamien Le Moal compatible = "canaan,k210", "riscv"; 5508734e05SDamien Le Moal reg = <1>; 5608734e05SDamien Le Moal riscv,isa = "rv64imafdc"; 5767d96729SDamien Le Moal mmu-type = "riscv,none"; 5808734e05SDamien Le Moal i-cache-block-size = <64>; 5967d96729SDamien Le Moal i-cache-size = <0x8000>; 6008734e05SDamien Le Moal d-cache-block-size = <64>; 6167d96729SDamien Le Moal d-cache-size = <0x8000>; 6208734e05SDamien Le Moal cpu1_intc: interrupt-controller { 6308734e05SDamien Le Moal #interrupt-cells = <1>; 6408734e05SDamien Le Moal interrupt-controller; 6508734e05SDamien Le Moal compatible = "riscv,cpu-intc"; 6608734e05SDamien Le Moal }; 6708734e05SDamien Le Moal }; 6808734e05SDamien Le Moal }; 6908734e05SDamien Le Moal 7008734e05SDamien Le Moal sram: memory@80000000 { 7108734e05SDamien Le Moal device_type = "memory"; 7267d96729SDamien Le Moal compatible = "canaan,k210-sram"; 7308734e05SDamien Le Moal reg = <0x80000000 0x400000>, 7408734e05SDamien Le Moal <0x80400000 0x200000>, 7508734e05SDamien Le Moal <0x80600000 0x200000>; 7608734e05SDamien Le Moal reg-names = "sram0", "sram1", "aisram"; 7767d96729SDamien Le Moal clocks = <&sysclk K210_CLK_SRAM0>, 7867d96729SDamien Le Moal <&sysclk K210_CLK_SRAM1>, 7967d96729SDamien Le Moal <&sysclk K210_CLK_AI>; 8067d96729SDamien Le Moal clock-names = "sram0", "sram1", "aisram"; 8108734e05SDamien Le Moal }; 8208734e05SDamien Le Moal 8308734e05SDamien Le Moal clocks { 8408734e05SDamien Le Moal in0: oscillator { 8508734e05SDamien Le Moal compatible = "fixed-clock"; 8608734e05SDamien Le Moal #clock-cells = <0>; 8708734e05SDamien Le Moal clock-frequency = <26000000>; 8808734e05SDamien Le Moal }; 8908734e05SDamien Le Moal }; 9008734e05SDamien Le Moal 9108734e05SDamien Le Moal soc { 9208734e05SDamien Le Moal #address-cells = <1>; 9308734e05SDamien Le Moal #size-cells = <1>; 9467d96729SDamien Le Moal compatible = "simple-bus"; 9508734e05SDamien Le Moal ranges; 9608734e05SDamien Le Moal interrupt-parent = <&plic0>; 9708734e05SDamien Le Moal 9867d96729SDamien Le Moal rom0: nvmem@1000 { 9967d96729SDamien Le Moal reg = <0x1000 0x1000>; 10067d96729SDamien Le Moal read-only; 10108734e05SDamien Le Moal }; 10208734e05SDamien Le Moal 10367d96729SDamien Le Moal clint0: timer@2000000 { 10467d96729SDamien Le Moal compatible = "canaan,k210-clint", "sifive,clint0"; 10508734e05SDamien Le Moal reg = <0x2000000 0xC000>; 106*75c0dc04SGeert Uytterhoeven interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 107*75c0dc04SGeert Uytterhoeven <&cpu1_intc 3>, <&cpu1_intc 7>; 10808734e05SDamien Le Moal }; 10908734e05SDamien Le Moal 11008734e05SDamien Le Moal plic0: interrupt-controller@c000000 { 11108734e05SDamien Le Moal #interrupt-cells = <1>; 11267d96729SDamien Le Moal #address-cells = <0>; 11367d96729SDamien Le Moal compatible = "canaan,k210-plic", "sifive,plic-1.0.0"; 11408734e05SDamien Le Moal reg = <0xC000000 0x4000000>; 11567d96729SDamien Le Moal interrupt-controller; 116*75c0dc04SGeert Uytterhoeven interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>; 11708734e05SDamien Le Moal riscv,ndev = <65>; 11808734e05SDamien Le Moal }; 11908734e05SDamien Le Moal 12008734e05SDamien Le Moal uarths0: serial@38000000 { 12167d96729SDamien Le Moal compatible = "canaan,k210-uarths", "sifive,uart0"; 12208734e05SDamien Le Moal reg = <0x38000000 0x1000>; 12308734e05SDamien Le Moal interrupts = <33>; 12467d96729SDamien Le Moal clocks = <&sysclk K210_CLK_CPU>; 12567d96729SDamien Le Moal }; 12667d96729SDamien Le Moal 12767d96729SDamien Le Moal gpio0: gpio-controller@38001000 { 12867d96729SDamien Le Moal #interrupt-cells = <2>; 12967d96729SDamien Le Moal #gpio-cells = <2>; 13067d96729SDamien Le Moal compatible = "canaan,k210-gpiohs", "sifive,gpio0"; 13167d96729SDamien Le Moal reg = <0x38001000 0x1000>; 13267d96729SDamien Le Moal interrupt-controller; 133*75c0dc04SGeert Uytterhoeven interrupts = <34>, <35>, <36>, <37>, <38>, <39>, <40>, 134*75c0dc04SGeert Uytterhoeven <41>, <42>, <43>, <44>, <45>, <46>, <47>, 135*75c0dc04SGeert Uytterhoeven <48>, <49>, <50>, <51>, <52>, <53>, <54>, 136*75c0dc04SGeert Uytterhoeven <55>, <56>, <57>, <58>, <59>, <60>, <61>, 137*75c0dc04SGeert Uytterhoeven <62>, <63>, <64>, <65>; 13867d96729SDamien Le Moal gpio-controller; 13967d96729SDamien Le Moal ngpios = <32>; 14067d96729SDamien Le Moal }; 14167d96729SDamien Le Moal 14267d96729SDamien Le Moal dmac0: dma-controller@50000000 { 14367d96729SDamien Le Moal compatible = "snps,axi-dma-1.01a"; 14467d96729SDamien Le Moal reg = <0x50000000 0x1000>; 145*75c0dc04SGeert Uytterhoeven interrupts = <27>, <28>, <29>, <30>, <31>, <32>; 14667d96729SDamien Le Moal #dma-cells = <1>; 14767d96729SDamien Le Moal clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; 14867d96729SDamien Le Moal clock-names = "core-clk", "cfgr-clk"; 14967d96729SDamien Le Moal resets = <&sysrst K210_RST_DMA>; 15067d96729SDamien Le Moal dma-channels = <6>; 15167d96729SDamien Le Moal snps,dma-masters = <2>; 15267d96729SDamien Le Moal snps,priority = <0 1 2 3 4 5>; 15367d96729SDamien Le Moal snps,data-width = <5>; 15467d96729SDamien Le Moal snps,block-size = <0x200000 0x200000 0x200000 15567d96729SDamien Le Moal 0x200000 0x200000 0x200000>; 15667d96729SDamien Le Moal snps,axi-max-burst-len = <256>; 15767d96729SDamien Le Moal }; 15867d96729SDamien Le Moal 15967d96729SDamien Le Moal apb0: bus@50200000 { 16067d96729SDamien Le Moal #address-cells = <1>; 16167d96729SDamien Le Moal #size-cells = <1>; 16267d96729SDamien Le Moal compatible = "simple-pm-bus"; 16367d96729SDamien Le Moal ranges; 16467d96729SDamien Le Moal clocks = <&sysclk K210_CLK_APB0>; 16567d96729SDamien Le Moal 16667d96729SDamien Le Moal gpio1: gpio@50200000 { 16767d96729SDamien Le Moal #address-cells = <1>; 16867d96729SDamien Le Moal #size-cells = <0>; 16967d96729SDamien Le Moal compatible = "snps,dw-apb-gpio"; 17067d96729SDamien Le Moal reg = <0x50200000 0x80>; 17167d96729SDamien Le Moal clocks = <&sysclk K210_CLK_APB0>, 17267d96729SDamien Le Moal <&sysclk K210_CLK_GPIO>; 17367d96729SDamien Le Moal clock-names = "bus", "db"; 17467d96729SDamien Le Moal resets = <&sysrst K210_RST_GPIO>; 17567d96729SDamien Le Moal 17667d96729SDamien Le Moal gpio1_0: gpio-port@0 { 17767d96729SDamien Le Moal #gpio-cells = <2>; 17867d96729SDamien Le Moal #interrupt-cells = <2>; 17967d96729SDamien Le Moal compatible = "snps,dw-apb-gpio-port"; 18067d96729SDamien Le Moal reg = <0>; 18167d96729SDamien Le Moal interrupt-controller; 18267d96729SDamien Le Moal interrupts = <23>; 18367d96729SDamien Le Moal gpio-controller; 18467d96729SDamien Le Moal ngpios = <8>; 18567d96729SDamien Le Moal }; 18667d96729SDamien Le Moal }; 18767d96729SDamien Le Moal 18867d96729SDamien Le Moal uart1: serial@50210000 { 18967d96729SDamien Le Moal compatible = "snps,dw-apb-uart"; 19067d96729SDamien Le Moal reg = <0x50210000 0x100>; 19167d96729SDamien Le Moal interrupts = <11>; 19267d96729SDamien Le Moal clocks = <&sysclk K210_CLK_UART1>, 19367d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 19467d96729SDamien Le Moal clock-names = "baudclk", "apb_pclk"; 19567d96729SDamien Le Moal resets = <&sysrst K210_RST_UART1>; 19667d96729SDamien Le Moal reg-io-width = <4>; 19767d96729SDamien Le Moal reg-shift = <2>; 19867d96729SDamien Le Moal dcd-override; 19967d96729SDamien Le Moal dsr-override; 20067d96729SDamien Le Moal cts-override; 20167d96729SDamien Le Moal ri-override; 20267d96729SDamien Le Moal }; 20367d96729SDamien Le Moal 20467d96729SDamien Le Moal uart2: serial@50220000 { 20567d96729SDamien Le Moal compatible = "snps,dw-apb-uart"; 20667d96729SDamien Le Moal reg = <0x50220000 0x100>; 20767d96729SDamien Le Moal interrupts = <12>; 20867d96729SDamien Le Moal clocks = <&sysclk K210_CLK_UART2>, 20967d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 21067d96729SDamien Le Moal clock-names = "baudclk", "apb_pclk"; 21167d96729SDamien Le Moal resets = <&sysrst K210_RST_UART2>; 21267d96729SDamien Le Moal reg-io-width = <4>; 21367d96729SDamien Le Moal reg-shift = <2>; 21467d96729SDamien Le Moal dcd-override; 21567d96729SDamien Le Moal dsr-override; 21667d96729SDamien Le Moal cts-override; 21767d96729SDamien Le Moal ri-override; 21867d96729SDamien Le Moal }; 21967d96729SDamien Le Moal 22067d96729SDamien Le Moal uart3: serial@50230000 { 22167d96729SDamien Le Moal compatible = "snps,dw-apb-uart"; 22267d96729SDamien Le Moal reg = <0x50230000 0x100>; 22367d96729SDamien Le Moal interrupts = <13>; 22467d96729SDamien Le Moal clocks = <&sysclk K210_CLK_UART3>, 22567d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 22667d96729SDamien Le Moal clock-names = "baudclk", "apb_pclk"; 22767d96729SDamien Le Moal resets = <&sysrst K210_RST_UART3>; 22867d96729SDamien Le Moal reg-io-width = <4>; 22967d96729SDamien Le Moal reg-shift = <2>; 23067d96729SDamien Le Moal dcd-override; 23167d96729SDamien Le Moal dsr-override; 23267d96729SDamien Le Moal cts-override; 23367d96729SDamien Le Moal ri-override; 23467d96729SDamien Le Moal }; 23567d96729SDamien Le Moal 23667d96729SDamien Le Moal spi2: spi@50240000 { 23767d96729SDamien Le Moal compatible = "canaan,k210-spi"; 23867d96729SDamien Le Moal spi-slave; 23967d96729SDamien Le Moal reg = <0x50240000 0x100>; 24067d96729SDamien Le Moal #address-cells = <0>; 24167d96729SDamien Le Moal #size-cells = <0>; 24267d96729SDamien Le Moal interrupts = <3>; 24367d96729SDamien Le Moal clocks = <&sysclk K210_CLK_SPI2>, 24467d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 24567d96729SDamien Le Moal clock-names = "ssi_clk", "pclk"; 24667d96729SDamien Le Moal resets = <&sysrst K210_RST_SPI2>; 24767d96729SDamien Le Moal spi-max-frequency = <25000000>; 24867d96729SDamien Le Moal }; 24967d96729SDamien Le Moal 25067d96729SDamien Le Moal i2s0: i2s@50250000 { 25167d96729SDamien Le Moal compatible = "snps,designware-i2s"; 25267d96729SDamien Le Moal reg = <0x50250000 0x200>; 25367d96729SDamien Le Moal interrupts = <5>; 25467d96729SDamien Le Moal clocks = <&sysclk K210_CLK_I2S0>; 25567d96729SDamien Le Moal clock-names = "i2sclk"; 25667d96729SDamien Le Moal resets = <&sysrst K210_RST_I2S0>; 25767d96729SDamien Le Moal }; 25867d96729SDamien Le Moal 25967d96729SDamien Le Moal i2s1: i2s@50260000 { 26067d96729SDamien Le Moal compatible = "snps,designware-i2s"; 26167d96729SDamien Le Moal reg = <0x50260000 0x200>; 26267d96729SDamien Le Moal interrupts = <6>; 26367d96729SDamien Le Moal clocks = <&sysclk K210_CLK_I2S1>; 26467d96729SDamien Le Moal clock-names = "i2sclk"; 26567d96729SDamien Le Moal resets = <&sysrst K210_RST_I2S1>; 26667d96729SDamien Le Moal }; 26767d96729SDamien Le Moal 26867d96729SDamien Le Moal i2s2: i2s@50270000 { 26967d96729SDamien Le Moal compatible = "snps,designware-i2s"; 27067d96729SDamien Le Moal reg = <0x50270000 0x200>; 27167d96729SDamien Le Moal interrupts = <7>; 27267d96729SDamien Le Moal clocks = <&sysclk K210_CLK_I2S2>; 27367d96729SDamien Le Moal clock-names = "i2sclk"; 27467d96729SDamien Le Moal resets = <&sysrst K210_RST_I2S2>; 27567d96729SDamien Le Moal }; 27667d96729SDamien Le Moal 27767d96729SDamien Le Moal i2c0: i2c@50280000 { 27867d96729SDamien Le Moal compatible = "snps,designware-i2c"; 27967d96729SDamien Le Moal reg = <0x50280000 0x100>; 28067d96729SDamien Le Moal interrupts = <8>; 28167d96729SDamien Le Moal clocks = <&sysclk K210_CLK_I2C0>, 28267d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 28367d96729SDamien Le Moal clock-names = "ref", "pclk"; 28467d96729SDamien Le Moal resets = <&sysrst K210_RST_I2C0>; 28567d96729SDamien Le Moal }; 28667d96729SDamien Le Moal 28767d96729SDamien Le Moal i2c1: i2c@50290000 { 28867d96729SDamien Le Moal compatible = "snps,designware-i2c"; 28967d96729SDamien Le Moal reg = <0x50290000 0x100>; 29067d96729SDamien Le Moal interrupts = <9>; 29167d96729SDamien Le Moal clocks = <&sysclk K210_CLK_I2C1>, 29267d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 29367d96729SDamien Le Moal clock-names = "ref", "pclk"; 29467d96729SDamien Le Moal resets = <&sysrst K210_RST_I2C1>; 29567d96729SDamien Le Moal }; 29667d96729SDamien Le Moal 29767d96729SDamien Le Moal i2c2: i2c@502a0000 { 29867d96729SDamien Le Moal compatible = "snps,designware-i2c"; 29967d96729SDamien Le Moal reg = <0x502A0000 0x100>; 30067d96729SDamien Le Moal interrupts = <10>; 30167d96729SDamien Le Moal clocks = <&sysclk K210_CLK_I2C2>, 30267d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 30367d96729SDamien Le Moal clock-names = "ref", "pclk"; 30467d96729SDamien Le Moal resets = <&sysrst K210_RST_I2C2>; 30567d96729SDamien Le Moal }; 30667d96729SDamien Le Moal 30767d96729SDamien Le Moal fpioa: pinmux@502b0000 { 30867d96729SDamien Le Moal compatible = "canaan,k210-fpioa"; 30967d96729SDamien Le Moal reg = <0x502B0000 0x100>; 31067d96729SDamien Le Moal clocks = <&sysclk K210_CLK_FPIOA>, 31167d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 31267d96729SDamien Le Moal clock-names = "ref", "pclk"; 31367d96729SDamien Le Moal resets = <&sysrst K210_RST_FPIOA>; 31467d96729SDamien Le Moal canaan,k210-sysctl-power = <&sysctl 108>; 31567d96729SDamien Le Moal }; 31667d96729SDamien Le Moal 31767d96729SDamien Le Moal timer0: timer@502d0000 { 31867d96729SDamien Le Moal compatible = "snps,dw-apb-timer"; 31967d96729SDamien Le Moal reg = <0x502D0000 0x100>; 320*75c0dc04SGeert Uytterhoeven interrupts = <14>, <15>; 32167d96729SDamien Le Moal clocks = <&sysclk K210_CLK_TIMER0>, 32267d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 32367d96729SDamien Le Moal clock-names = "timer", "pclk"; 32467d96729SDamien Le Moal resets = <&sysrst K210_RST_TIMER0>; 32567d96729SDamien Le Moal }; 32667d96729SDamien Le Moal 32767d96729SDamien Le Moal timer1: timer@502e0000 { 32867d96729SDamien Le Moal compatible = "snps,dw-apb-timer"; 32967d96729SDamien Le Moal reg = <0x502E0000 0x100>; 330*75c0dc04SGeert Uytterhoeven interrupts = <16>, <17>; 33167d96729SDamien Le Moal clocks = <&sysclk K210_CLK_TIMER1>, 33267d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 33367d96729SDamien Le Moal clock-names = "timer", "pclk"; 33467d96729SDamien Le Moal resets = <&sysrst K210_RST_TIMER1>; 33567d96729SDamien Le Moal }; 33667d96729SDamien Le Moal 33767d96729SDamien Le Moal timer2: timer@502f0000 { 33867d96729SDamien Le Moal compatible = "snps,dw-apb-timer"; 33967d96729SDamien Le Moal reg = <0x502F0000 0x100>; 340*75c0dc04SGeert Uytterhoeven interrupts = <18>, <19>; 34167d96729SDamien Le Moal clocks = <&sysclk K210_CLK_TIMER2>, 34267d96729SDamien Le Moal <&sysclk K210_CLK_APB0>; 34367d96729SDamien Le Moal clock-names = "timer", "pclk"; 34467d96729SDamien Le Moal resets = <&sysrst K210_RST_TIMER2>; 34567d96729SDamien Le Moal }; 34667d96729SDamien Le Moal }; 34767d96729SDamien Le Moal 34867d96729SDamien Le Moal apb1: bus@50400000 { 34967d96729SDamien Le Moal #address-cells = <1>; 35067d96729SDamien Le Moal #size-cells = <1>; 35167d96729SDamien Le Moal compatible = "simple-pm-bus"; 35267d96729SDamien Le Moal ranges; 35367d96729SDamien Le Moal clocks = <&sysclk K210_CLK_APB1>; 35467d96729SDamien Le Moal 35567d96729SDamien Le Moal wdt0: watchdog@50400000 { 35667d96729SDamien Le Moal compatible = "snps,dw-wdt"; 35767d96729SDamien Le Moal reg = <0x50400000 0x100>; 35867d96729SDamien Le Moal interrupts = <21>; 35967d96729SDamien Le Moal clocks = <&sysclk K210_CLK_WDT0>, 36067d96729SDamien Le Moal <&sysclk K210_CLK_APB1>; 36167d96729SDamien Le Moal clock-names = "tclk", "pclk"; 36267d96729SDamien Le Moal resets = <&sysrst K210_RST_WDT0>; 36367d96729SDamien Le Moal }; 36467d96729SDamien Le Moal 36567d96729SDamien Le Moal wdt1: watchdog@50410000 { 36667d96729SDamien Le Moal compatible = "snps,dw-wdt"; 36767d96729SDamien Le Moal reg = <0x50410000 0x100>; 36867d96729SDamien Le Moal interrupts = <22>; 36967d96729SDamien Le Moal clocks = <&sysclk K210_CLK_WDT1>, 37067d96729SDamien Le Moal <&sysclk K210_CLK_APB1>; 37167d96729SDamien Le Moal clock-names = "tclk", "pclk"; 37267d96729SDamien Le Moal resets = <&sysrst K210_RST_WDT1>; 37367d96729SDamien Le Moal }; 37467d96729SDamien Le Moal 37567d96729SDamien Le Moal sysctl: syscon@50440000 { 37667d96729SDamien Le Moal compatible = "canaan,k210-sysctl", 37767d96729SDamien Le Moal "syscon", "simple-mfd"; 37867d96729SDamien Le Moal reg = <0x50440000 0x100>; 37967d96729SDamien Le Moal clocks = <&sysclk K210_CLK_APB1>; 38067d96729SDamien Le Moal clock-names = "pclk"; 38167d96729SDamien Le Moal 38267d96729SDamien Le Moal sysclk: clock-controller { 38367d96729SDamien Le Moal #clock-cells = <1>; 38467d96729SDamien Le Moal compatible = "canaan,k210-clk"; 38567d96729SDamien Le Moal clocks = <&in0>; 38667d96729SDamien Le Moal }; 38767d96729SDamien Le Moal 38867d96729SDamien Le Moal sysrst: reset-controller { 38967d96729SDamien Le Moal compatible = "canaan,k210-rst"; 39067d96729SDamien Le Moal #reset-cells = <1>; 39167d96729SDamien Le Moal }; 39267d96729SDamien Le Moal 39367d96729SDamien Le Moal reboot: syscon-reboot { 39467d96729SDamien Le Moal compatible = "syscon-reboot"; 39567d96729SDamien Le Moal regmap = <&sysctl>; 39667d96729SDamien Le Moal offset = <48>; 39767d96729SDamien Le Moal mask = <1>; 39867d96729SDamien Le Moal value = <1>; 39967d96729SDamien Le Moal }; 40067d96729SDamien Le Moal }; 40167d96729SDamien Le Moal }; 40267d96729SDamien Le Moal 40367d96729SDamien Le Moal apb2: bus@52000000 { 40467d96729SDamien Le Moal #address-cells = <1>; 40567d96729SDamien Le Moal #size-cells = <1>; 40667d96729SDamien Le Moal compatible = "simple-pm-bus"; 40767d96729SDamien Le Moal ranges; 40867d96729SDamien Le Moal clocks = <&sysclk K210_CLK_APB2>; 40967d96729SDamien Le Moal 41067d96729SDamien Le Moal spi0: spi@52000000 { 41167d96729SDamien Le Moal #address-cells = <1>; 41267d96729SDamien Le Moal #size-cells = <0>; 41367d96729SDamien Le Moal compatible = "canaan,k210-spi"; 41467d96729SDamien Le Moal reg = <0x52000000 0x100>; 41567d96729SDamien Le Moal interrupts = <1>; 41667d96729SDamien Le Moal clocks = <&sysclk K210_CLK_SPI0>, 41767d96729SDamien Le Moal <&sysclk K210_CLK_APB2>; 41867d96729SDamien Le Moal clock-names = "ssi_clk", "pclk"; 41967d96729SDamien Le Moal resets = <&sysrst K210_RST_SPI0>; 42067d96729SDamien Le Moal reset-names = "spi"; 42167d96729SDamien Le Moal spi-max-frequency = <25000000>; 42267d96729SDamien Le Moal num-cs = <4>; 42367d96729SDamien Le Moal reg-io-width = <4>; 42467d96729SDamien Le Moal }; 42567d96729SDamien Le Moal 42667d96729SDamien Le Moal spi1: spi@53000000 { 42767d96729SDamien Le Moal #address-cells = <1>; 42867d96729SDamien Le Moal #size-cells = <0>; 42967d96729SDamien Le Moal compatible = "canaan,k210-spi"; 43067d96729SDamien Le Moal reg = <0x53000000 0x100>; 43167d96729SDamien Le Moal interrupts = <2>; 43267d96729SDamien Le Moal clocks = <&sysclk K210_CLK_SPI1>, 43367d96729SDamien Le Moal <&sysclk K210_CLK_APB2>; 43467d96729SDamien Le Moal clock-names = "ssi_clk", "pclk"; 43567d96729SDamien Le Moal resets = <&sysrst K210_RST_SPI1>; 43667d96729SDamien Le Moal reset-names = "spi"; 43767d96729SDamien Le Moal spi-max-frequency = <25000000>; 43867d96729SDamien Le Moal num-cs = <4>; 43967d96729SDamien Le Moal reg-io-width = <4>; 44067d96729SDamien Le Moal }; 44167d96729SDamien Le Moal 44267d96729SDamien Le Moal spi3: spi@54000000 { 44367d96729SDamien Le Moal #address-cells = <1>; 44467d96729SDamien Le Moal #size-cells = <0>; 44567d96729SDamien Le Moal compatible = "snps,dwc-ssi-1.01a"; 44667d96729SDamien Le Moal reg = <0x54000000 0x200>; 44767d96729SDamien Le Moal interrupts = <4>; 44867d96729SDamien Le Moal clocks = <&sysclk K210_CLK_SPI3>, 44967d96729SDamien Le Moal <&sysclk K210_CLK_APB2>; 45067d96729SDamien Le Moal clock-names = "ssi_clk", "pclk"; 45167d96729SDamien Le Moal resets = <&sysrst K210_RST_SPI3>; 45267d96729SDamien Le Moal reset-names = "spi"; 45367d96729SDamien Le Moal /* Could possibly go up to 200 MHz */ 45467d96729SDamien Le Moal spi-max-frequency = <100000000>; 45567d96729SDamien Le Moal num-cs = <4>; 45667d96729SDamien Le Moal reg-io-width = <4>; 45767d96729SDamien Le Moal }; 45808734e05SDamien Le Moal }; 45908734e05SDamien Le Moal }; 46008734e05SDamien Le Moal}; 461