1// SPDX-License-Identifier: (GPL-2.0+ or MIT) 2// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> 3 4#include <dt-bindings/clock/sun6i-rtc.h> 5#include <dt-bindings/clock/sun8i-de2.h> 6#include <dt-bindings/clock/sun8i-tcon-top.h> 7#include <dt-bindings/clock/sun20i-d1-ccu.h> 8#include <dt-bindings/clock/sun20i-d1-r-ccu.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/reset/sun8i-de2.h> 11#include <dt-bindings/reset/sun20i-d1-ccu.h> 12#include <dt-bindings/reset/sun20i-d1-r-ccu.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 dcxo: dcxo-clk { 19 compatible = "fixed-clock"; 20 clock-output-names = "dcxo"; 21 #clock-cells = <0>; 22 }; 23 24 de: display-engine { 25 compatible = "allwinner,sun20i-d1-display-engine"; 26 allwinner,pipelines = <&mixer0>, <&mixer1>; 27 status = "disabled"; 28 }; 29 30 soc { 31 compatible = "simple-bus"; 32 ranges; 33 dma-noncoherent; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 37 pio: pinctrl@2000000 { 38 compatible = "allwinner,sun20i-d1-pinctrl"; 39 reg = <0x2000000 0x800>; 40 interrupts = <SOC_PERIPHERAL_IRQ(69) IRQ_TYPE_LEVEL_HIGH>, 41 <SOC_PERIPHERAL_IRQ(71) IRQ_TYPE_LEVEL_HIGH>, 42 <SOC_PERIPHERAL_IRQ(73) IRQ_TYPE_LEVEL_HIGH>, 43 <SOC_PERIPHERAL_IRQ(75) IRQ_TYPE_LEVEL_HIGH>, 44 <SOC_PERIPHERAL_IRQ(77) IRQ_TYPE_LEVEL_HIGH>, 45 <SOC_PERIPHERAL_IRQ(79) IRQ_TYPE_LEVEL_HIGH>; 46 clocks = <&ccu CLK_APB0>, 47 <&dcxo>, 48 <&rtc CLK_OSC32K>; 49 clock-names = "apb", "hosc", "losc"; 50 gpio-controller; 51 interrupt-controller; 52 #gpio-cells = <3>; 53 #interrupt-cells = <3>; 54 55 /omit-if-no-ref/ 56 clk_pg11_pin: clk-pg11-pin { 57 pins = "PG11"; 58 function = "clk"; 59 }; 60 61 /omit-if-no-ref/ 62 dsi_4lane_pins: dsi-4lane-pins { 63 pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", 64 "PD6", "PD7", "PD8", "PD9"; 65 drive-strength = <30>; 66 function = "dsi"; 67 }; 68 69 /omit-if-no-ref/ 70 lcd_rgb666_pins: lcd-rgb666-pins { 71 pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", 72 "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", 73 "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", 74 "PD18", "PD19", "PD20", "PD21"; 75 function = "lcd0"; 76 }; 77 78 /omit-if-no-ref/ 79 mmc0_pins: mmc0-pins { 80 pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; 81 function = "mmc0"; 82 }; 83 84 /omit-if-no-ref/ 85 mmc1_pins: mmc1-pins { 86 pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; 87 function = "mmc1"; 88 }; 89 90 /omit-if-no-ref/ 91 mmc2_pins: mmc2-pins { 92 pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; 93 function = "mmc2"; 94 }; 95 96 /omit-if-no-ref/ 97 rgmii_pe_pins: rgmii-pe-pins { 98 pins = "PE0", "PE1", "PE2", "PE3", "PE4", 99 "PE5", "PE6", "PE7", "PE8", "PE9", 100 "PE11", "PE12", "PE13", "PE14", "PE15"; 101 function = "emac"; 102 }; 103 104 /omit-if-no-ref/ 105 rmii_pe_pins: rmii-pe-pins { 106 pins = "PE0", "PE1", "PE2", "PE3", "PE4", 107 "PE5", "PE6", "PE7", "PE8", "PE9"; 108 function = "emac"; 109 }; 110 111 /omit-if-no-ref/ 112 uart1_pg6_pins: uart1-pg6-pins { 113 pins = "PG6", "PG7"; 114 function = "uart1"; 115 }; 116 117 /omit-if-no-ref/ 118 uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins { 119 pins = "PG8", "PG9"; 120 function = "uart1"; 121 }; 122 123 /omit-if-no-ref/ 124 uart3_pb_pins: uart3-pb-pins { 125 pins = "PB6", "PB7"; 126 function = "uart3"; 127 }; 128 }; 129 130 ccu: clock-controller@2001000 { 131 compatible = "allwinner,sun20i-d1-ccu"; 132 reg = <0x2001000 0x1000>; 133 clocks = <&dcxo>, 134 <&rtc CLK_OSC32K>, 135 <&rtc CLK_IOSC>; 136 clock-names = "hosc", "losc", "iosc"; 137 #clock-cells = <1>; 138 #reset-cells = <1>; 139 }; 140 141 dmic: dmic@2031000 { 142 compatible = "allwinner,sun20i-d1-dmic", 143 "allwinner,sun50i-h6-dmic"; 144 reg = <0x2031000 0x400>; 145 interrupts = <SOC_PERIPHERAL_IRQ(24) IRQ_TYPE_LEVEL_HIGH>; 146 clocks = <&ccu CLK_BUS_DMIC>, 147 <&ccu CLK_DMIC>; 148 clock-names = "bus", "mod"; 149 resets = <&ccu RST_BUS_DMIC>; 150 dmas = <&dma 8>; 151 dma-names = "rx"; 152 status = "disabled"; 153 #sound-dai-cells = <0>; 154 }; 155 156 i2s1: i2s@2033000 { 157 compatible = "allwinner,sun20i-d1-i2s", 158 "allwinner,sun50i-r329-i2s"; 159 reg = <0x2033000 0x1000>; 160 interrupts = <SOC_PERIPHERAL_IRQ(27) IRQ_TYPE_LEVEL_HIGH>; 161 clocks = <&ccu CLK_BUS_I2S1>, 162 <&ccu CLK_I2S1>; 163 clock-names = "apb", "mod"; 164 resets = <&ccu RST_BUS_I2S1>; 165 dmas = <&dma 4>, <&dma 4>; 166 dma-names = "rx", "tx"; 167 status = "disabled"; 168 #sound-dai-cells = <0>; 169 }; 170 171 i2s2: i2s@2034000 { 172 compatible = "allwinner,sun20i-d1-i2s", 173 "allwinner,sun50i-r329-i2s"; 174 reg = <0x2034000 0x1000>; 175 interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>; 176 clocks = <&ccu CLK_BUS_I2S2>, 177 <&ccu CLK_I2S2>; 178 clock-names = "apb", "mod"; 179 resets = <&ccu RST_BUS_I2S2>; 180 dmas = <&dma 5>, <&dma 5>; 181 dma-names = "rx", "tx"; 182 status = "disabled"; 183 #sound-dai-cells = <0>; 184 }; 185 186 timer: timer@2050000 { 187 compatible = "allwinner,sun20i-d1-timer", 188 "allwinner,sun8i-a23-timer"; 189 reg = <0x2050000 0xa0>; 190 interrupts = <SOC_PERIPHERAL_IRQ(59) IRQ_TYPE_LEVEL_HIGH>, 191 <SOC_PERIPHERAL_IRQ(60) IRQ_TYPE_LEVEL_HIGH>; 192 clocks = <&dcxo>; 193 }; 194 195 wdt: watchdog@20500a0 { 196 compatible = "allwinner,sun20i-d1-wdt-reset", 197 "allwinner,sun20i-d1-wdt"; 198 reg = <0x20500a0 0x20>; 199 interrupts = <SOC_PERIPHERAL_IRQ(63) IRQ_TYPE_LEVEL_HIGH>; 200 clocks = <&dcxo>, <&rtc CLK_OSC32K>; 201 clock-names = "hosc", "losc"; 202 status = "reserved"; 203 }; 204 205 uart0: serial@2500000 { 206 compatible = "snps,dw-apb-uart"; 207 reg = <0x2500000 0x400>; 208 reg-io-width = <4>; 209 reg-shift = <2>; 210 interrupts = <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&ccu CLK_BUS_UART0>; 212 resets = <&ccu RST_BUS_UART0>; 213 dmas = <&dma 14>, <&dma 14>; 214 dma-names = "tx", "rx"; 215 status = "disabled"; 216 }; 217 218 uart1: serial@2500400 { 219 compatible = "snps,dw-apb-uart"; 220 reg = <0x2500400 0x400>; 221 reg-io-width = <4>; 222 reg-shift = <2>; 223 interrupts = <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&ccu CLK_BUS_UART1>; 225 resets = <&ccu RST_BUS_UART1>; 226 dmas = <&dma 15>, <&dma 15>; 227 dma-names = "tx", "rx"; 228 status = "disabled"; 229 }; 230 231 uart2: serial@2500800 { 232 compatible = "snps,dw-apb-uart"; 233 reg = <0x2500800 0x400>; 234 reg-io-width = <4>; 235 reg-shift = <2>; 236 interrupts = <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&ccu CLK_BUS_UART2>; 238 resets = <&ccu RST_BUS_UART2>; 239 dmas = <&dma 16>, <&dma 16>; 240 dma-names = "tx", "rx"; 241 status = "disabled"; 242 }; 243 244 uart3: serial@2500c00 { 245 compatible = "snps,dw-apb-uart"; 246 reg = <0x2500c00 0x400>; 247 reg-io-width = <4>; 248 reg-shift = <2>; 249 interrupts = <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&ccu CLK_BUS_UART3>; 251 resets = <&ccu RST_BUS_UART3>; 252 dmas = <&dma 17>, <&dma 17>; 253 dma-names = "tx", "rx"; 254 status = "disabled"; 255 }; 256 257 uart4: serial@2501000 { 258 compatible = "snps,dw-apb-uart"; 259 reg = <0x2501000 0x400>; 260 reg-io-width = <4>; 261 reg-shift = <2>; 262 interrupts = <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&ccu CLK_BUS_UART4>; 264 resets = <&ccu RST_BUS_UART4>; 265 dmas = <&dma 18>, <&dma 18>; 266 dma-names = "tx", "rx"; 267 status = "disabled"; 268 }; 269 270 uart5: serial@2501400 { 271 compatible = "snps,dw-apb-uart"; 272 reg = <0x2501400 0x400>; 273 reg-io-width = <4>; 274 reg-shift = <2>; 275 interrupts = <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&ccu CLK_BUS_UART5>; 277 resets = <&ccu RST_BUS_UART5>; 278 dmas = <&dma 19>, <&dma 19>; 279 dma-names = "tx", "rx"; 280 status = "disabled"; 281 }; 282 283 i2c0: i2c@2502000 { 284 compatible = "allwinner,sun20i-d1-i2c", 285 "allwinner,sun8i-v536-i2c", 286 "allwinner,sun6i-a31-i2c"; 287 reg = <0x2502000 0x400>; 288 interrupts = <SOC_PERIPHERAL_IRQ(9) IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&ccu CLK_BUS_I2C0>; 290 resets = <&ccu RST_BUS_I2C0>; 291 dmas = <&dma 43>, <&dma 43>; 292 dma-names = "rx", "tx"; 293 status = "disabled"; 294 #address-cells = <1>; 295 #size-cells = <0>; 296 }; 297 298 i2c1: i2c@2502400 { 299 compatible = "allwinner,sun20i-d1-i2c", 300 "allwinner,sun8i-v536-i2c", 301 "allwinner,sun6i-a31-i2c"; 302 reg = <0x2502400 0x400>; 303 interrupts = <SOC_PERIPHERAL_IRQ(10) IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&ccu CLK_BUS_I2C1>; 305 resets = <&ccu RST_BUS_I2C1>; 306 dmas = <&dma 44>, <&dma 44>; 307 dma-names = "rx", "tx"; 308 status = "disabled"; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 }; 312 313 i2c2: i2c@2502800 { 314 compatible = "allwinner,sun20i-d1-i2c", 315 "allwinner,sun8i-v536-i2c", 316 "allwinner,sun6i-a31-i2c"; 317 reg = <0x2502800 0x400>; 318 interrupts = <SOC_PERIPHERAL_IRQ(11) IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&ccu CLK_BUS_I2C2>; 320 resets = <&ccu RST_BUS_I2C2>; 321 dmas = <&dma 45>, <&dma 45>; 322 dma-names = "rx", "tx"; 323 status = "disabled"; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 }; 327 328 i2c3: i2c@2502c00 { 329 compatible = "allwinner,sun20i-d1-i2c", 330 "allwinner,sun8i-v536-i2c", 331 "allwinner,sun6i-a31-i2c"; 332 reg = <0x2502c00 0x400>; 333 interrupts = <SOC_PERIPHERAL_IRQ(12) IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&ccu CLK_BUS_I2C3>; 335 resets = <&ccu RST_BUS_I2C3>; 336 dmas = <&dma 46>, <&dma 46>; 337 dma-names = "rx", "tx"; 338 status = "disabled"; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 }; 342 343 syscon: syscon@3000000 { 344 compatible = "allwinner,sun20i-d1-system-control"; 345 reg = <0x3000000 0x1000>; 346 ranges; 347 #address-cells = <1>; 348 #size-cells = <1>; 349 }; 350 351 dma: dma-controller@3002000 { 352 compatible = "allwinner,sun20i-d1-dma"; 353 reg = <0x3002000 0x1000>; 354 interrupts = <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 356 clock-names = "bus", "mbus"; 357 resets = <&ccu RST_BUS_DMA>; 358 dma-channels = <16>; 359 dma-requests = <48>; 360 #dma-cells = <1>; 361 }; 362 363 sid: efuse@3006000 { 364 compatible = "allwinner,sun20i-d1-sid"; 365 reg = <0x3006000 0x1000>; 366 #address-cells = <1>; 367 #size-cells = <1>; 368 }; 369 370 crypto: crypto@3040000 { 371 compatible = "allwinner,sun20i-d1-crypto"; 372 reg = <0x3040000 0x800>; 373 interrupts = <SOC_PERIPHERAL_IRQ(52) IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&ccu CLK_BUS_CE>, 375 <&ccu CLK_CE>, 376 <&ccu CLK_MBUS_CE>, 377 <&rtc CLK_IOSC>; 378 clock-names = "bus", "mod", "ram", "trng"; 379 resets = <&ccu RST_BUS_CE>; 380 }; 381 382 mbus: dram-controller@3102000 { 383 compatible = "allwinner,sun20i-d1-mbus"; 384 reg = <0x3102000 0x1000>, 385 <0x3103000 0x1000>; 386 reg-names = "mbus", "dram"; 387 interrupts = <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&ccu CLK_MBUS>, 389 <&ccu CLK_DRAM>, 390 <&ccu CLK_BUS_DRAM>; 391 clock-names = "mbus", "dram", "bus"; 392 dma-ranges = <0 0x40000000 0x80000000>; 393 #address-cells = <1>; 394 #size-cells = <1>; 395 #interconnect-cells = <1>; 396 }; 397 398 mmc0: mmc@4020000 { 399 compatible = "allwinner,sun20i-d1-mmc"; 400 reg = <0x4020000 0x1000>; 401 interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 403 clock-names = "ahb", "mmc"; 404 resets = <&ccu RST_BUS_MMC0>; 405 reset-names = "ahb"; 406 cap-sd-highspeed; 407 max-frequency = <150000000>; 408 no-mmc; 409 status = "disabled"; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 }; 413 414 mmc1: mmc@4021000 { 415 compatible = "allwinner,sun20i-d1-mmc"; 416 reg = <0x4021000 0x1000>; 417 interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 419 clock-names = "ahb", "mmc"; 420 resets = <&ccu RST_BUS_MMC1>; 421 reset-names = "ahb"; 422 cap-sd-highspeed; 423 max-frequency = <150000000>; 424 no-mmc; 425 status = "disabled"; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 }; 429 430 mmc2: mmc@4022000 { 431 compatible = "allwinner,sun20i-d1-emmc", 432 "allwinner,sun50i-a100-emmc"; 433 reg = <0x4022000 0x1000>; 434 interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 436 clock-names = "ahb", "mmc"; 437 resets = <&ccu RST_BUS_MMC2>; 438 reset-names = "ahb"; 439 cap-mmc-highspeed; 440 max-frequency = <150000000>; 441 mmc-ddr-1_8v; 442 mmc-ddr-3_3v; 443 no-sd; 444 no-sdio; 445 status = "disabled"; 446 #address-cells = <1>; 447 #size-cells = <0>; 448 }; 449 450 usb_otg: usb@4100000 { 451 compatible = "allwinner,sun20i-d1-musb", 452 "allwinner,sun8i-a33-musb"; 453 reg = <0x4100000 0x400>; 454 interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>; 455 interrupt-names = "mc"; 456 clocks = <&ccu CLK_BUS_OTG>; 457 resets = <&ccu RST_BUS_OTG>; 458 extcon = <&usbphy 0>; 459 phys = <&usbphy 0>; 460 phy-names = "usb"; 461 status = "disabled"; 462 }; 463 464 usbphy: phy@4100400 { 465 compatible = "allwinner,sun20i-d1-usb-phy"; 466 reg = <0x4100400 0x100>, 467 <0x4101800 0x100>, 468 <0x4200800 0x100>; 469 reg-names = "phy_ctrl", 470 "pmu0", 471 "pmu1"; 472 clocks = <&dcxo>, 473 <&dcxo>; 474 clock-names = "usb0_phy", 475 "usb1_phy"; 476 resets = <&ccu RST_USB_PHY0>, 477 <&ccu RST_USB_PHY1>; 478 reset-names = "usb0_reset", 479 "usb1_reset"; 480 status = "disabled"; 481 #phy-cells = <1>; 482 }; 483 484 ehci0: usb@4101000 { 485 compatible = "allwinner,sun20i-d1-ehci", 486 "generic-ehci"; 487 reg = <0x4101000 0x100>; 488 interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&ccu CLK_BUS_OHCI0>, 490 <&ccu CLK_BUS_EHCI0>, 491 <&ccu CLK_USB_OHCI0>; 492 resets = <&ccu RST_BUS_OHCI0>, 493 <&ccu RST_BUS_EHCI0>; 494 phys = <&usbphy 0>; 495 phy-names = "usb"; 496 status = "disabled"; 497 }; 498 499 ohci0: usb@4101400 { 500 compatible = "allwinner,sun20i-d1-ohci", 501 "generic-ohci"; 502 reg = <0x4101400 0x100>; 503 interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&ccu CLK_BUS_OHCI0>, 505 <&ccu CLK_USB_OHCI0>; 506 resets = <&ccu RST_BUS_OHCI0>; 507 phys = <&usbphy 0>; 508 phy-names = "usb"; 509 status = "disabled"; 510 }; 511 512 ehci1: usb@4200000 { 513 compatible = "allwinner,sun20i-d1-ehci", 514 "generic-ehci"; 515 reg = <0x4200000 0x100>; 516 interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&ccu CLK_BUS_OHCI1>, 518 <&ccu CLK_BUS_EHCI1>, 519 <&ccu CLK_USB_OHCI1>; 520 resets = <&ccu RST_BUS_OHCI1>, 521 <&ccu RST_BUS_EHCI1>; 522 phys = <&usbphy 1>; 523 phy-names = "usb"; 524 status = "disabled"; 525 }; 526 527 ohci1: usb@4200400 { 528 compatible = "allwinner,sun20i-d1-ohci", 529 "generic-ohci"; 530 reg = <0x4200400 0x100>; 531 interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&ccu CLK_BUS_OHCI1>, 533 <&ccu CLK_USB_OHCI1>; 534 resets = <&ccu RST_BUS_OHCI1>; 535 phys = <&usbphy 1>; 536 phy-names = "usb"; 537 status = "disabled"; 538 }; 539 540 emac: ethernet@4500000 { 541 compatible = "allwinner,sun20i-d1-emac", 542 "allwinner,sun50i-a64-emac"; 543 reg = <0x4500000 0x10000>; 544 interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>; 545 interrupt-names = "macirq"; 546 clocks = <&ccu CLK_BUS_EMAC>; 547 clock-names = "stmmaceth"; 548 resets = <&ccu RST_BUS_EMAC>; 549 reset-names = "stmmaceth"; 550 syscon = <&syscon>; 551 status = "disabled"; 552 553 mdio: mdio { 554 compatible = "snps,dwmac-mdio"; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 }; 558 }; 559 560 display_clocks: clock-controller@5000000 { 561 compatible = "allwinner,sun20i-d1-de2-clk", 562 "allwinner,sun50i-h5-de2-clk"; 563 reg = <0x5000000 0x10000>; 564 clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; 565 clock-names = "bus", "mod"; 566 resets = <&ccu RST_BUS_DE>; 567 #clock-cells = <1>; 568 #reset-cells = <1>; 569 }; 570 571 mixer0: mixer@5100000 { 572 compatible = "allwinner,sun20i-d1-de2-mixer-0"; 573 reg = <0x5100000 0x100000>; 574 clocks = <&display_clocks CLK_BUS_MIXER0>, 575 <&display_clocks CLK_MIXER0>; 576 clock-names = "bus", "mod"; 577 resets = <&display_clocks RST_MIXER0>; 578 579 ports { 580 #address-cells = <1>; 581 #size-cells = <0>; 582 583 mixer0_out: port@1 { 584 reg = <1>; 585 586 mixer0_out_tcon_top_mixer0: endpoint { 587 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 588 }; 589 }; 590 }; 591 }; 592 593 mixer1: mixer@5200000 { 594 compatible = "allwinner,sun20i-d1-de2-mixer-1"; 595 reg = <0x5200000 0x100000>; 596 clocks = <&display_clocks CLK_BUS_MIXER1>, 597 <&display_clocks CLK_MIXER1>; 598 clock-names = "bus", "mod"; 599 resets = <&display_clocks RST_MIXER1>; 600 601 ports { 602 #address-cells = <1>; 603 #size-cells = <0>; 604 605 mixer1_out: port@1 { 606 reg = <1>; 607 608 mixer1_out_tcon_top_mixer1: endpoint { 609 remote-endpoint = <&tcon_top_mixer1_in_mixer1>; 610 }; 611 }; 612 }; 613 }; 614 615 dsi: dsi@5450000 { 616 compatible = "allwinner,sun20i-d1-mipi-dsi", 617 "allwinner,sun50i-a100-mipi-dsi"; 618 reg = <0x5450000 0x1000>; 619 interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&ccu CLK_BUS_MIPI_DSI>, 621 <&tcon_top CLK_TCON_TOP_DSI>; 622 clock-names = "bus", "mod"; 623 resets = <&ccu RST_BUS_MIPI_DSI>; 624 phys = <&dphy>; 625 phy-names = "dphy"; 626 status = "disabled"; 627 628 port { 629 dsi_in_tcon_lcd0: endpoint { 630 remote-endpoint = <&tcon_lcd0_out_dsi>; 631 }; 632 }; 633 }; 634 635 dphy: phy@5451000 { 636 compatible = "allwinner,sun20i-d1-mipi-dphy", 637 "allwinner,sun50i-a100-mipi-dphy"; 638 reg = <0x5451000 0x1000>; 639 interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&ccu CLK_BUS_MIPI_DSI>, 641 <&ccu CLK_MIPI_DSI>; 642 clock-names = "bus", "mod"; 643 resets = <&ccu RST_BUS_MIPI_DSI>; 644 #phy-cells = <0>; 645 }; 646 647 tcon_top: tcon-top@5460000 { 648 compatible = "allwinner,sun20i-d1-tcon-top"; 649 reg = <0x5460000 0x1000>; 650 clocks = <&ccu CLK_BUS_DPSS_TOP>, 651 <&ccu CLK_TCON_TV>, 652 <&ccu CLK_TVE>, 653 <&ccu CLK_TCON_LCD0>; 654 clock-names = "bus", "tcon-tv0", "tve0", "dsi"; 655 clock-output-names = "tcon-top-tv0", "tcon-top-dsi"; 656 resets = <&ccu RST_BUS_DPSS_TOP>; 657 #clock-cells = <1>; 658 659 ports { 660 #address-cells = <1>; 661 #size-cells = <0>; 662 663 tcon_top_mixer0_in: port@0 { 664 reg = <0>; 665 666 tcon_top_mixer0_in_mixer0: endpoint { 667 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 668 }; 669 }; 670 671 tcon_top_mixer0_out: port@1 { 672 reg = <1>; 673 #address-cells = <1>; 674 #size-cells = <0>; 675 676 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { 677 reg = <0>; 678 remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>; 679 }; 680 681 tcon_top_mixer0_out_tcon_tv0: endpoint@2 { 682 reg = <2>; 683 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; 684 }; 685 }; 686 687 tcon_top_mixer1_in: port@2 { 688 reg = <2>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 692 tcon_top_mixer1_in_mixer1: endpoint@1 { 693 reg = <1>; 694 remote-endpoint = <&mixer1_out_tcon_top_mixer1>; 695 }; 696 }; 697 698 tcon_top_mixer1_out: port@3 { 699 reg = <3>; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 703 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { 704 reg = <0>; 705 remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>; 706 }; 707 708 tcon_top_mixer1_out_tcon_tv0: endpoint@2 { 709 reg = <2>; 710 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; 711 }; 712 }; 713 714 tcon_top_hdmi_in: port@4 { 715 reg = <4>; 716 717 tcon_top_hdmi_in_tcon_tv0: endpoint { 718 remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>; 719 }; 720 }; 721 722 tcon_top_hdmi_out: port@5 { 723 reg = <5>; 724 }; 725 }; 726 }; 727 728 tcon_lcd0: lcd-controller@5461000 { 729 compatible = "allwinner,sun20i-d1-tcon-lcd"; 730 reg = <0x5461000 0x1000>; 731 interrupts = <SOC_PERIPHERAL_IRQ(90) IRQ_TYPE_LEVEL_HIGH>; 732 clocks = <&ccu CLK_BUS_TCON_LCD0>, 733 <&ccu CLK_TCON_LCD0>; 734 clock-names = "ahb", "tcon-ch0"; 735 clock-output-names = "tcon-pixel-clock"; 736 resets = <&ccu RST_BUS_TCON_LCD0>, 737 <&ccu RST_BUS_LVDS0>; 738 reset-names = "lcd", "lvds"; 739 #clock-cells = <0>; 740 741 ports { 742 #address-cells = <1>; 743 #size-cells = <0>; 744 745 tcon_lcd0_in: port@0 { 746 reg = <0>; 747 #address-cells = <1>; 748 #size-cells = <0>; 749 750 tcon_lcd0_in_tcon_top_mixer0: endpoint@0 { 751 reg = <0>; 752 remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>; 753 }; 754 755 tcon_lcd0_in_tcon_top_mixer1: endpoint@1 { 756 reg = <1>; 757 remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>; 758 }; 759 }; 760 761 tcon_lcd0_out: port@1 { 762 reg = <1>; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 766 tcon_lcd0_out_dsi: endpoint@1 { 767 reg = <1>; 768 remote-endpoint = <&dsi_in_tcon_lcd0>; 769 }; 770 }; 771 }; 772 }; 773 774 tcon_tv0: lcd-controller@5470000 { 775 compatible = "allwinner,sun20i-d1-tcon-tv"; 776 reg = <0x5470000 0x1000>; 777 interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>; 778 clocks = <&ccu CLK_BUS_TCON_TV>, 779 <&tcon_top CLK_TCON_TOP_TV0>; 780 clock-names = "ahb", "tcon-ch1"; 781 resets = <&ccu RST_BUS_TCON_TV>; 782 reset-names = "lcd"; 783 784 ports { 785 #address-cells = <1>; 786 #size-cells = <0>; 787 788 tcon_tv0_in: port@0 { 789 reg = <0>; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 793 tcon_tv0_in_tcon_top_mixer0: endpoint@0 { 794 reg = <0>; 795 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; 796 }; 797 798 tcon_tv0_in_tcon_top_mixer1: endpoint@1 { 799 reg = <1>; 800 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; 801 }; 802 }; 803 804 tcon_tv0_out: port@1 { 805 reg = <1>; 806 807 tcon_tv0_out_tcon_top_hdmi: endpoint { 808 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; 809 }; 810 }; 811 }; 812 }; 813 814 ppu: power-controller@7001000 { 815 compatible = "allwinner,sun20i-d1-ppu"; 816 reg = <0x7001000 0x1000>; 817 clocks = <&r_ccu CLK_BUS_R_PPU>; 818 resets = <&r_ccu RST_BUS_R_PPU>; 819 #power-domain-cells = <1>; 820 }; 821 822 r_ccu: clock-controller@7010000 { 823 compatible = "allwinner,sun20i-d1-r-ccu"; 824 reg = <0x7010000 0x400>; 825 clocks = <&dcxo>, 826 <&rtc CLK_OSC32K>, 827 <&rtc CLK_IOSC>, 828 <&ccu CLK_PLL_PERIPH0_DIV3>; 829 clock-names = "hosc", "losc", "iosc", "pll-periph"; 830 #clock-cells = <1>; 831 #reset-cells = <1>; 832 }; 833 834 rtc: rtc@7090000 { 835 compatible = "allwinner,sun20i-d1-rtc", 836 "allwinner,sun50i-r329-rtc"; 837 reg = <0x7090000 0x400>; 838 interrupts = <SOC_PERIPHERAL_IRQ(144) IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&r_ccu CLK_BUS_R_RTC>, 840 <&dcxo>, 841 <&r_ccu CLK_R_AHB>; 842 clock-names = "bus", "hosc", "ahb"; 843 #clock-cells = <1>; 844 }; 845 }; 846}; 847