1// SPDX-License-Identifier: (GPL-2.0+ or MIT) 2// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> 3 4#include <dt-bindings/clock/sun6i-rtc.h> 5#include <dt-bindings/clock/sun8i-de2.h> 6#include <dt-bindings/clock/sun8i-tcon-top.h> 7#include <dt-bindings/clock/sun20i-d1-ccu.h> 8#include <dt-bindings/clock/sun20i-d1-r-ccu.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/reset/sun8i-de2.h> 11#include <dt-bindings/reset/sun20i-d1-ccu.h> 12#include <dt-bindings/reset/sun20i-d1-r-ccu.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 dcxo: dcxo-clk { 19 compatible = "fixed-clock"; 20 clock-output-names = "dcxo"; 21 #clock-cells = <0>; 22 }; 23 24 de: display-engine { 25 compatible = "allwinner,sun20i-d1-display-engine"; 26 allwinner,pipelines = <&mixer0>, <&mixer1>; 27 status = "disabled"; 28 }; 29 30 soc { 31 compatible = "simple-bus"; 32 ranges; 33 dma-noncoherent; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 37 pio: pinctrl@2000000 { 38 compatible = "allwinner,sun20i-d1-pinctrl"; 39 reg = <0x2000000 0x800>; 40 interrupts = <SOC_PERIPHERAL_IRQ(69) IRQ_TYPE_LEVEL_HIGH>, 41 <SOC_PERIPHERAL_IRQ(71) IRQ_TYPE_LEVEL_HIGH>, 42 <SOC_PERIPHERAL_IRQ(73) IRQ_TYPE_LEVEL_HIGH>, 43 <SOC_PERIPHERAL_IRQ(75) IRQ_TYPE_LEVEL_HIGH>, 44 <SOC_PERIPHERAL_IRQ(77) IRQ_TYPE_LEVEL_HIGH>, 45 <SOC_PERIPHERAL_IRQ(79) IRQ_TYPE_LEVEL_HIGH>; 46 clocks = <&ccu CLK_APB0>, 47 <&dcxo>, 48 <&rtc CLK_OSC32K>; 49 clock-names = "apb", "hosc", "losc"; 50 gpio-controller; 51 interrupt-controller; 52 #gpio-cells = <3>; 53 #interrupt-cells = <3>; 54 55 /omit-if-no-ref/ 56 clk_pg11_pin: clk-pg11-pin { 57 pins = "PG11"; 58 function = "clk"; 59 }; 60 61 /omit-if-no-ref/ 62 dsi_4lane_pins: dsi-4lane-pins { 63 pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", 64 "PD6", "PD7", "PD8", "PD9"; 65 drive-strength = <30>; 66 function = "dsi"; 67 }; 68 69 /omit-if-no-ref/ 70 lcd_rgb666_pins: lcd-rgb666-pins { 71 pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", 72 "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", 73 "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", 74 "PD18", "PD19", "PD20", "PD21"; 75 function = "lcd0"; 76 }; 77 78 /omit-if-no-ref/ 79 mmc0_pins: mmc0-pins { 80 pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; 81 function = "mmc0"; 82 }; 83 84 /omit-if-no-ref/ 85 mmc1_pins: mmc1-pins { 86 pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; 87 function = "mmc1"; 88 }; 89 90 /omit-if-no-ref/ 91 mmc2_pins: mmc2-pins { 92 pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; 93 function = "mmc2"; 94 }; 95 96 /omit-if-no-ref/ 97 rgmii_pe_pins: rgmii-pe-pins { 98 pins = "PE0", "PE1", "PE2", "PE3", "PE4", 99 "PE5", "PE6", "PE7", "PE8", "PE9", 100 "PE11", "PE12", "PE13", "PE14", "PE15"; 101 function = "emac"; 102 }; 103 104 /omit-if-no-ref/ 105 rmii_pe_pins: rmii-pe-pins { 106 pins = "PE0", "PE1", "PE2", "PE3", "PE4", 107 "PE5", "PE6", "PE7", "PE8", "PE9"; 108 function = "emac"; 109 }; 110 111 /omit-if-no-ref/ 112 uart1_pg6_pins: uart1-pg6-pins { 113 pins = "PG6", "PG7"; 114 function = "uart1"; 115 }; 116 117 /omit-if-no-ref/ 118 uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins { 119 pins = "PG8", "PG9"; 120 function = "uart1"; 121 }; 122 123 /omit-if-no-ref/ 124 uart3_pb_pins: uart3-pb-pins { 125 pins = "PB6", "PB7"; 126 function = "uart3"; 127 }; 128 }; 129 130 ccu: clock-controller@2001000 { 131 compatible = "allwinner,sun20i-d1-ccu"; 132 reg = <0x2001000 0x1000>; 133 clocks = <&dcxo>, 134 <&rtc CLK_OSC32K>, 135 <&rtc CLK_IOSC>; 136 clock-names = "hosc", "losc", "iosc"; 137 #clock-cells = <1>; 138 #reset-cells = <1>; 139 }; 140 141 dmic: dmic@2031000 { 142 compatible = "allwinner,sun20i-d1-dmic", 143 "allwinner,sun50i-h6-dmic"; 144 reg = <0x2031000 0x400>; 145 interrupts = <SOC_PERIPHERAL_IRQ(24) IRQ_TYPE_LEVEL_HIGH>; 146 clocks = <&ccu CLK_BUS_DMIC>, 147 <&ccu CLK_DMIC>; 148 clock-names = "bus", "mod"; 149 resets = <&ccu RST_BUS_DMIC>; 150 dmas = <&dma 8>; 151 dma-names = "rx"; 152 status = "disabled"; 153 #sound-dai-cells = <0>; 154 }; 155 156 i2s1: i2s@2033000 { 157 compatible = "allwinner,sun20i-d1-i2s", 158 "allwinner,sun50i-r329-i2s"; 159 reg = <0x2033000 0x1000>; 160 interrupts = <SOC_PERIPHERAL_IRQ(27) IRQ_TYPE_LEVEL_HIGH>; 161 clocks = <&ccu CLK_BUS_I2S1>, 162 <&ccu CLK_I2S1>; 163 clock-names = "apb", "mod"; 164 resets = <&ccu RST_BUS_I2S1>; 165 dmas = <&dma 4>, <&dma 4>; 166 dma-names = "rx", "tx"; 167 status = "disabled"; 168 #sound-dai-cells = <0>; 169 }; 170 171 i2s2: i2s@2034000 { 172 compatible = "allwinner,sun20i-d1-i2s", 173 "allwinner,sun50i-r329-i2s"; 174 reg = <0x2034000 0x1000>; 175 interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>; 176 clocks = <&ccu CLK_BUS_I2S2>, 177 <&ccu CLK_I2S2>; 178 clock-names = "apb", "mod"; 179 resets = <&ccu RST_BUS_I2S2>; 180 dmas = <&dma 5>, <&dma 5>; 181 dma-names = "rx", "tx"; 182 status = "disabled"; 183 #sound-dai-cells = <0>; 184 }; 185 186 timer: timer@2050000 { 187 compatible = "allwinner,sun20i-d1-timer", 188 "allwinner,sun8i-a23-timer"; 189 reg = <0x2050000 0xa0>; 190 interrupts = <SOC_PERIPHERAL_IRQ(59) IRQ_TYPE_LEVEL_HIGH>, 191 <SOC_PERIPHERAL_IRQ(60) IRQ_TYPE_LEVEL_HIGH>; 192 clocks = <&dcxo>; 193 }; 194 195 wdt: watchdog@20500a0 { 196 compatible = "allwinner,sun20i-d1-wdt-reset", 197 "allwinner,sun20i-d1-wdt"; 198 reg = <0x20500a0 0x20>; 199 interrupts = <SOC_PERIPHERAL_IRQ(63) IRQ_TYPE_LEVEL_HIGH>; 200 clocks = <&dcxo>, <&rtc CLK_OSC32K>; 201 clock-names = "hosc", "losc"; 202 status = "reserved"; 203 }; 204 205 uart0: serial@2500000 { 206 compatible = "snps,dw-apb-uart"; 207 reg = <0x2500000 0x400>; 208 reg-io-width = <4>; 209 reg-shift = <2>; 210 interrupts = <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&ccu CLK_BUS_UART0>; 212 resets = <&ccu RST_BUS_UART0>; 213 dmas = <&dma 14>, <&dma 14>; 214 dma-names = "rx", "tx"; 215 status = "disabled"; 216 }; 217 218 uart1: serial@2500400 { 219 compatible = "snps,dw-apb-uart"; 220 reg = <0x2500400 0x400>; 221 reg-io-width = <4>; 222 reg-shift = <2>; 223 interrupts = <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&ccu CLK_BUS_UART1>; 225 resets = <&ccu RST_BUS_UART1>; 226 dmas = <&dma 15>, <&dma 15>; 227 dma-names = "rx", "tx"; 228 status = "disabled"; 229 }; 230 231 uart2: serial@2500800 { 232 compatible = "snps,dw-apb-uart"; 233 reg = <0x2500800 0x400>; 234 reg-io-width = <4>; 235 reg-shift = <2>; 236 interrupts = <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&ccu CLK_BUS_UART2>; 238 resets = <&ccu RST_BUS_UART2>; 239 dmas = <&dma 16>, <&dma 16>; 240 dma-names = "rx", "tx"; 241 status = "disabled"; 242 }; 243 244 uart3: serial@2500c00 { 245 compatible = "snps,dw-apb-uart"; 246 reg = <0x2500c00 0x400>; 247 reg-io-width = <4>; 248 reg-shift = <2>; 249 interrupts = <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&ccu CLK_BUS_UART3>; 251 resets = <&ccu RST_BUS_UART3>; 252 dmas = <&dma 17>, <&dma 17>; 253 dma-names = "rx", "tx"; 254 status = "disabled"; 255 }; 256 257 uart4: serial@2501000 { 258 compatible = "snps,dw-apb-uart"; 259 reg = <0x2501000 0x400>; 260 reg-io-width = <4>; 261 reg-shift = <2>; 262 interrupts = <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&ccu CLK_BUS_UART4>; 264 resets = <&ccu RST_BUS_UART4>; 265 dmas = <&dma 18>, <&dma 18>; 266 dma-names = "rx", "tx"; 267 status = "disabled"; 268 }; 269 270 uart5: serial@2501400 { 271 compatible = "snps,dw-apb-uart"; 272 reg = <0x2501400 0x400>; 273 reg-io-width = <4>; 274 reg-shift = <2>; 275 interrupts = <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&ccu CLK_BUS_UART5>; 277 resets = <&ccu RST_BUS_UART5>; 278 dmas = <&dma 19>, <&dma 19>; 279 dma-names = "rx", "tx"; 280 status = "disabled"; 281 }; 282 283 i2c0: i2c@2502000 { 284 compatible = "allwinner,sun20i-d1-i2c", 285 "allwinner,sun8i-v536-i2c", 286 "allwinner,sun6i-a31-i2c"; 287 reg = <0x2502000 0x400>; 288 interrupts = <SOC_PERIPHERAL_IRQ(9) IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&ccu CLK_BUS_I2C0>; 290 resets = <&ccu RST_BUS_I2C0>; 291 dmas = <&dma 43>, <&dma 43>; 292 dma-names = "rx", "tx"; 293 status = "disabled"; 294 #address-cells = <1>; 295 #size-cells = <0>; 296 }; 297 298 i2c1: i2c@2502400 { 299 compatible = "allwinner,sun20i-d1-i2c", 300 "allwinner,sun8i-v536-i2c", 301 "allwinner,sun6i-a31-i2c"; 302 reg = <0x2502400 0x400>; 303 interrupts = <SOC_PERIPHERAL_IRQ(10) IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&ccu CLK_BUS_I2C1>; 305 resets = <&ccu RST_BUS_I2C1>; 306 dmas = <&dma 44>, <&dma 44>; 307 dma-names = "rx", "tx"; 308 status = "disabled"; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 }; 312 313 i2c2: i2c@2502800 { 314 compatible = "allwinner,sun20i-d1-i2c", 315 "allwinner,sun8i-v536-i2c", 316 "allwinner,sun6i-a31-i2c"; 317 reg = <0x2502800 0x400>; 318 interrupts = <SOC_PERIPHERAL_IRQ(11) IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&ccu CLK_BUS_I2C2>; 320 resets = <&ccu RST_BUS_I2C2>; 321 dmas = <&dma 45>, <&dma 45>; 322 dma-names = "rx", "tx"; 323 status = "disabled"; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 }; 327 328 i2c3: i2c@2502c00 { 329 compatible = "allwinner,sun20i-d1-i2c", 330 "allwinner,sun8i-v536-i2c", 331 "allwinner,sun6i-a31-i2c"; 332 reg = <0x2502c00 0x400>; 333 interrupts = <SOC_PERIPHERAL_IRQ(12) IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&ccu CLK_BUS_I2C3>; 335 resets = <&ccu RST_BUS_I2C3>; 336 dmas = <&dma 46>, <&dma 46>; 337 dma-names = "rx", "tx"; 338 status = "disabled"; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 }; 342 343 syscon: syscon@3000000 { 344 compatible = "allwinner,sun20i-d1-system-control"; 345 reg = <0x3000000 0x1000>; 346 ranges; 347 #address-cells = <1>; 348 #size-cells = <1>; 349 }; 350 351 dma: dma-controller@3002000 { 352 compatible = "allwinner,sun20i-d1-dma"; 353 reg = <0x3002000 0x1000>; 354 interrupts = <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 356 clock-names = "bus", "mbus"; 357 resets = <&ccu RST_BUS_DMA>; 358 dma-channels = <16>; 359 dma-requests = <48>; 360 #dma-cells = <1>; 361 }; 362 363 sid: efuse@3006000 { 364 compatible = "allwinner,sun20i-d1-sid"; 365 reg = <0x3006000 0x1000>; 366 #address-cells = <1>; 367 #size-cells = <1>; 368 }; 369 370 mbus: dram-controller@3102000 { 371 compatible = "allwinner,sun20i-d1-mbus"; 372 reg = <0x3102000 0x1000>, 373 <0x3103000 0x1000>; 374 reg-names = "mbus", "dram"; 375 interrupts = <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&ccu CLK_MBUS>, 377 <&ccu CLK_DRAM>, 378 <&ccu CLK_BUS_DRAM>; 379 clock-names = "mbus", "dram", "bus"; 380 dma-ranges = <0 0x40000000 0x80000000>; 381 #address-cells = <1>; 382 #size-cells = <1>; 383 #interconnect-cells = <1>; 384 }; 385 386 mmc0: mmc@4020000 { 387 compatible = "allwinner,sun20i-d1-mmc"; 388 reg = <0x4020000 0x1000>; 389 interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 391 clock-names = "ahb", "mmc"; 392 resets = <&ccu RST_BUS_MMC0>; 393 reset-names = "ahb"; 394 cap-sd-highspeed; 395 max-frequency = <150000000>; 396 no-mmc; 397 status = "disabled"; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 }; 401 402 mmc1: mmc@4021000 { 403 compatible = "allwinner,sun20i-d1-mmc"; 404 reg = <0x4021000 0x1000>; 405 interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 407 clock-names = "ahb", "mmc"; 408 resets = <&ccu RST_BUS_MMC1>; 409 reset-names = "ahb"; 410 cap-sd-highspeed; 411 max-frequency = <150000000>; 412 no-mmc; 413 status = "disabled"; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 }; 417 418 mmc2: mmc@4022000 { 419 compatible = "allwinner,sun20i-d1-emmc", 420 "allwinner,sun50i-a100-emmc"; 421 reg = <0x4022000 0x1000>; 422 interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>; 423 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 424 clock-names = "ahb", "mmc"; 425 resets = <&ccu RST_BUS_MMC2>; 426 reset-names = "ahb"; 427 cap-mmc-highspeed; 428 max-frequency = <150000000>; 429 mmc-ddr-1_8v; 430 mmc-ddr-3_3v; 431 no-sd; 432 no-sdio; 433 status = "disabled"; 434 #address-cells = <1>; 435 #size-cells = <0>; 436 }; 437 438 usb_otg: usb@4100000 { 439 compatible = "allwinner,sun20i-d1-musb", 440 "allwinner,sun8i-a33-musb"; 441 reg = <0x4100000 0x400>; 442 interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>; 443 interrupt-names = "mc"; 444 clocks = <&ccu CLK_BUS_OTG>; 445 resets = <&ccu RST_BUS_OTG>; 446 extcon = <&usbphy 0>; 447 phys = <&usbphy 0>; 448 phy-names = "usb"; 449 status = "disabled"; 450 }; 451 452 usbphy: phy@4100400 { 453 compatible = "allwinner,sun20i-d1-usb-phy"; 454 reg = <0x4100400 0x100>, 455 <0x4101800 0x100>, 456 <0x4200800 0x100>; 457 reg-names = "phy_ctrl", 458 "pmu0", 459 "pmu1"; 460 clocks = <&dcxo>, 461 <&dcxo>; 462 clock-names = "usb0_phy", 463 "usb1_phy"; 464 resets = <&ccu RST_USB_PHY0>, 465 <&ccu RST_USB_PHY1>; 466 reset-names = "usb0_reset", 467 "usb1_reset"; 468 status = "disabled"; 469 #phy-cells = <1>; 470 }; 471 472 ehci0: usb@4101000 { 473 compatible = "allwinner,sun20i-d1-ehci", 474 "generic-ehci"; 475 reg = <0x4101000 0x100>; 476 interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&ccu CLK_BUS_OHCI0>, 478 <&ccu CLK_BUS_EHCI0>, 479 <&ccu CLK_USB_OHCI0>; 480 resets = <&ccu RST_BUS_OHCI0>, 481 <&ccu RST_BUS_EHCI0>; 482 phys = <&usbphy 0>; 483 phy-names = "usb"; 484 status = "disabled"; 485 }; 486 487 ohci0: usb@4101400 { 488 compatible = "allwinner,sun20i-d1-ohci", 489 "generic-ohci"; 490 reg = <0x4101400 0x100>; 491 interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&ccu CLK_BUS_OHCI0>, 493 <&ccu CLK_USB_OHCI0>; 494 resets = <&ccu RST_BUS_OHCI0>; 495 phys = <&usbphy 0>; 496 phy-names = "usb"; 497 status = "disabled"; 498 }; 499 500 ehci1: usb@4200000 { 501 compatible = "allwinner,sun20i-d1-ehci", 502 "generic-ehci"; 503 reg = <0x4200000 0x100>; 504 interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&ccu CLK_BUS_OHCI1>, 506 <&ccu CLK_BUS_EHCI1>, 507 <&ccu CLK_USB_OHCI1>; 508 resets = <&ccu RST_BUS_OHCI1>, 509 <&ccu RST_BUS_EHCI1>; 510 phys = <&usbphy 1>; 511 phy-names = "usb"; 512 status = "disabled"; 513 }; 514 515 ohci1: usb@4200400 { 516 compatible = "allwinner,sun20i-d1-ohci", 517 "generic-ohci"; 518 reg = <0x4200400 0x100>; 519 interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&ccu CLK_BUS_OHCI1>, 521 <&ccu CLK_USB_OHCI1>; 522 resets = <&ccu RST_BUS_OHCI1>; 523 phys = <&usbphy 1>; 524 phy-names = "usb"; 525 status = "disabled"; 526 }; 527 528 emac: ethernet@4500000 { 529 compatible = "allwinner,sun20i-d1-emac", 530 "allwinner,sun50i-a64-emac"; 531 reg = <0x4500000 0x10000>; 532 interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>; 533 interrupt-names = "macirq"; 534 clocks = <&ccu CLK_BUS_EMAC>; 535 clock-names = "stmmaceth"; 536 resets = <&ccu RST_BUS_EMAC>; 537 reset-names = "stmmaceth"; 538 syscon = <&syscon>; 539 status = "disabled"; 540 541 mdio: mdio { 542 compatible = "snps,dwmac-mdio"; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 }; 546 }; 547 548 display_clocks: clock-controller@5000000 { 549 compatible = "allwinner,sun20i-d1-de2-clk", 550 "allwinner,sun50i-h5-de2-clk"; 551 reg = <0x5000000 0x10000>; 552 clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; 553 clock-names = "bus", "mod"; 554 resets = <&ccu RST_BUS_DE>; 555 #clock-cells = <1>; 556 #reset-cells = <1>; 557 }; 558 559 mixer0: mixer@5100000 { 560 compatible = "allwinner,sun20i-d1-de2-mixer-0"; 561 reg = <0x5100000 0x100000>; 562 clocks = <&display_clocks CLK_BUS_MIXER0>, 563 <&display_clocks CLK_MIXER0>; 564 clock-names = "bus", "mod"; 565 resets = <&display_clocks RST_MIXER0>; 566 567 ports { 568 #address-cells = <1>; 569 #size-cells = <0>; 570 571 mixer0_out: port@1 { 572 reg = <1>; 573 574 mixer0_out_tcon_top_mixer0: endpoint { 575 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 576 }; 577 }; 578 }; 579 }; 580 581 mixer1: mixer@5200000 { 582 compatible = "allwinner,sun20i-d1-de2-mixer-1"; 583 reg = <0x5200000 0x100000>; 584 clocks = <&display_clocks CLK_BUS_MIXER1>, 585 <&display_clocks CLK_MIXER1>; 586 clock-names = "bus", "mod"; 587 resets = <&display_clocks RST_MIXER1>; 588 589 ports { 590 #address-cells = <1>; 591 #size-cells = <0>; 592 593 mixer1_out: port@1 { 594 reg = <1>; 595 596 mixer1_out_tcon_top_mixer1: endpoint { 597 remote-endpoint = <&tcon_top_mixer1_in_mixer1>; 598 }; 599 }; 600 }; 601 }; 602 603 dsi: dsi@5450000 { 604 compatible = "allwinner,sun20i-d1-mipi-dsi", 605 "allwinner,sun50i-a100-mipi-dsi"; 606 reg = <0x5450000 0x1000>; 607 interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&ccu CLK_BUS_MIPI_DSI>, 609 <&tcon_top CLK_TCON_TOP_DSI>; 610 clock-names = "bus", "mod"; 611 resets = <&ccu RST_BUS_MIPI_DSI>; 612 phys = <&dphy>; 613 phy-names = "dphy"; 614 status = "disabled"; 615 616 port { 617 dsi_in_tcon_lcd0: endpoint { 618 remote-endpoint = <&tcon_lcd0_out_dsi>; 619 }; 620 }; 621 }; 622 623 dphy: phy@5451000 { 624 compatible = "allwinner,sun20i-d1-mipi-dphy", 625 "allwinner,sun50i-a100-mipi-dphy"; 626 reg = <0x5451000 0x1000>; 627 interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&ccu CLK_BUS_MIPI_DSI>, 629 <&ccu CLK_MIPI_DSI>; 630 clock-names = "bus", "mod"; 631 resets = <&ccu RST_BUS_MIPI_DSI>; 632 #phy-cells = <0>; 633 }; 634 635 tcon_top: tcon-top@5460000 { 636 compatible = "allwinner,sun20i-d1-tcon-top"; 637 reg = <0x5460000 0x1000>; 638 clocks = <&ccu CLK_BUS_DPSS_TOP>, 639 <&ccu CLK_TCON_TV>, 640 <&ccu CLK_TVE>, 641 <&ccu CLK_TCON_LCD0>; 642 clock-names = "bus", "tcon-tv0", "tve0", "dsi"; 643 clock-output-names = "tcon-top-tv0", "tcon-top-dsi"; 644 resets = <&ccu RST_BUS_DPSS_TOP>; 645 #clock-cells = <1>; 646 647 ports { 648 #address-cells = <1>; 649 #size-cells = <0>; 650 651 tcon_top_mixer0_in: port@0 { 652 reg = <0>; 653 654 tcon_top_mixer0_in_mixer0: endpoint { 655 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 656 }; 657 }; 658 659 tcon_top_mixer0_out: port@1 { 660 reg = <1>; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 664 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { 665 reg = <0>; 666 remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>; 667 }; 668 669 tcon_top_mixer0_out_tcon_tv0: endpoint@2 { 670 reg = <2>; 671 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; 672 }; 673 }; 674 675 tcon_top_mixer1_in: port@2 { 676 reg = <2>; 677 #address-cells = <1>; 678 #size-cells = <0>; 679 680 tcon_top_mixer1_in_mixer1: endpoint@1 { 681 reg = <1>; 682 remote-endpoint = <&mixer1_out_tcon_top_mixer1>; 683 }; 684 }; 685 686 tcon_top_mixer1_out: port@3 { 687 reg = <3>; 688 #address-cells = <1>; 689 #size-cells = <0>; 690 691 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { 692 reg = <0>; 693 remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>; 694 }; 695 696 tcon_top_mixer1_out_tcon_tv0: endpoint@2 { 697 reg = <2>; 698 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; 699 }; 700 }; 701 702 tcon_top_hdmi_in: port@4 { 703 reg = <4>; 704 705 tcon_top_hdmi_in_tcon_tv0: endpoint { 706 remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>; 707 }; 708 }; 709 710 tcon_top_hdmi_out: port@5 { 711 reg = <5>; 712 }; 713 }; 714 }; 715 716 tcon_lcd0: lcd-controller@5461000 { 717 compatible = "allwinner,sun20i-d1-tcon-lcd"; 718 reg = <0x5461000 0x1000>; 719 interrupts = <SOC_PERIPHERAL_IRQ(90) IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&ccu CLK_BUS_TCON_LCD0>, 721 <&ccu CLK_TCON_LCD0>; 722 clock-names = "ahb", "tcon-ch0"; 723 clock-output-names = "tcon-pixel-clock"; 724 resets = <&ccu RST_BUS_TCON_LCD0>, 725 <&ccu RST_BUS_LVDS0>; 726 reset-names = "lcd", "lvds"; 727 #clock-cells = <0>; 728 729 ports { 730 #address-cells = <1>; 731 #size-cells = <0>; 732 733 tcon_lcd0_in: port@0 { 734 reg = <0>; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 738 tcon_lcd0_in_tcon_top_mixer0: endpoint@0 { 739 reg = <0>; 740 remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>; 741 }; 742 743 tcon_lcd0_in_tcon_top_mixer1: endpoint@1 { 744 reg = <1>; 745 remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>; 746 }; 747 }; 748 749 tcon_lcd0_out: port@1 { 750 reg = <1>; 751 #address-cells = <1>; 752 #size-cells = <0>; 753 754 tcon_lcd0_out_dsi: endpoint@1 { 755 reg = <1>; 756 remote-endpoint = <&dsi_in_tcon_lcd0>; 757 }; 758 }; 759 }; 760 }; 761 762 tcon_tv0: lcd-controller@5470000 { 763 compatible = "allwinner,sun20i-d1-tcon-tv"; 764 reg = <0x5470000 0x1000>; 765 interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&ccu CLK_BUS_TCON_TV>, 767 <&tcon_top CLK_TCON_TOP_TV0>; 768 clock-names = "ahb", "tcon-ch1"; 769 resets = <&ccu RST_BUS_TCON_TV>; 770 reset-names = "lcd"; 771 772 ports { 773 #address-cells = <1>; 774 #size-cells = <0>; 775 776 tcon_tv0_in: port@0 { 777 reg = <0>; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 781 tcon_tv0_in_tcon_top_mixer0: endpoint@0 { 782 reg = <0>; 783 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; 784 }; 785 786 tcon_tv0_in_tcon_top_mixer1: endpoint@1 { 787 reg = <1>; 788 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; 789 }; 790 }; 791 792 tcon_tv0_out: port@1 { 793 reg = <1>; 794 795 tcon_tv0_out_tcon_top_hdmi: endpoint { 796 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; 797 }; 798 }; 799 }; 800 }; 801 802 ppu: power-controller@7001000 { 803 compatible = "allwinner,sun20i-d1-ppu"; 804 reg = <0x7001000 0x1000>; 805 clocks = <&r_ccu CLK_BUS_R_PPU>; 806 resets = <&r_ccu RST_BUS_R_PPU>; 807 #power-domain-cells = <1>; 808 }; 809 810 r_ccu: clock-controller@7010000 { 811 compatible = "allwinner,sun20i-d1-r-ccu"; 812 reg = <0x7010000 0x400>; 813 clocks = <&dcxo>, 814 <&rtc CLK_OSC32K>, 815 <&rtc CLK_IOSC>, 816 <&ccu CLK_PLL_PERIPH0_DIV3>; 817 clock-names = "hosc", "losc", "iosc", "pll-periph"; 818 #clock-cells = <1>; 819 #reset-cells = <1>; 820 }; 821 822 rtc: rtc@7090000 { 823 compatible = "allwinner,sun20i-d1-rtc", 824 "allwinner,sun50i-r329-rtc"; 825 reg = <0x7090000 0x400>; 826 interrupts = <SOC_PERIPHERAL_IRQ(144) IRQ_TYPE_LEVEL_HIGH>; 827 clocks = <&r_ccu CLK_BUS_R_RTC>, 828 <&dcxo>, 829 <&r_ccu CLK_R_AHB>; 830 clock-names = "bus", "hosc", "ahb"; 831 #clock-cells = <1>; 832 }; 833 }; 834}; 835