xref: /openbmc/linux/arch/riscv/Kconfig.errata (revision 3ddc8b84) 
1menu "CPU errata selection"
2
3config ERRATA_ANDES
4	bool "Andes AX45MP errata"
5	depends on RISCV_ALTERNATIVE && RISCV_SBI
6	help
7	  All Andes errata Kconfig depend on this Kconfig. Disabling
8	  this Kconfig will disable all Andes errata. Please say "Y"
9	  here if your platform uses Andes CPU cores.
10
11	  Otherwise, please say "N" here to avoid unnecessary overhead.
12
13config ERRATA_ANDES_CMO
14	bool "Apply Andes cache management errata"
15	depends on ERRATA_ANDES && ARCH_R9A07G043
16	select RISCV_DMA_NONCOHERENT
17	default y
18	help
19	  This will apply the cache management errata to handle the
20	  non-standard handling on non-coherent operations on Andes cores.
21
22	  If you don't know what to do here, say "Y".
23
24config ERRATA_SIFIVE
25	bool "SiFive errata"
26	depends on RISCV_ALTERNATIVE
27	help
28	  All SiFive errata Kconfig depend on this Kconfig. Disabling
29	  this Kconfig will disable all SiFive errata. Please say "Y"
30	  here if your platform uses SiFive CPU cores.
31
32	  Otherwise, please say "N" here to avoid unnecessary overhead.
33
34config ERRATA_SIFIVE_CIP_453
35	bool "Apply SiFive errata CIP-453"
36	depends on ERRATA_SIFIVE && 64BIT
37	default y
38	help
39	  This will apply the SiFive CIP-453 errata to add sign extension
40	  to the $badaddr when exception type is instruction page fault
41	  and instruction access fault.
42
43	  If you don't know what to do here, say "Y".
44
45config ERRATA_SIFIVE_CIP_1200
46	bool "Apply SiFive errata CIP-1200"
47	depends on ERRATA_SIFIVE && 64BIT
48	default y
49	help
50	  This will apply the SiFive CIP-1200 errata to repalce all
51	  "sfence.vma addr" with "sfence.vma" to ensure that the addr
52	  has been flushed from TLB.
53
54	  If you don't know what to do here, say "Y".
55
56config ERRATA_THEAD
57	bool "T-HEAD errata"
58	depends on RISCV_ALTERNATIVE
59	help
60	  All T-HEAD errata Kconfig depend on this Kconfig. Disabling
61	  this Kconfig will disable all T-HEAD errata. Please say "Y"
62	  here if your platform uses T-HEAD CPU cores.
63
64	  Otherwise, please say "N" here to avoid unnecessary overhead.
65
66config ERRATA_THEAD_PBMT
67	bool "Apply T-Head memory type errata"
68	depends on ERRATA_THEAD && 64BIT && MMU
69	select RISCV_ALTERNATIVE_EARLY
70	default y
71	help
72	  This will apply the memory type errata to handle the non-standard
73	  memory type bits in page-table-entries on T-Head SoCs.
74
75	  If you don't know what to do here, say "Y".
76
77config ERRATA_THEAD_CMO
78	bool "Apply T-Head cache management errata"
79	depends on ERRATA_THEAD && MMU
80	select DMA_DIRECT_REMAP
81	select RISCV_DMA_NONCOHERENT
82	default y
83	help
84	  This will apply the cache management errata to handle the
85	  non-standard handling on non-coherent operations on T-Head SoCs.
86
87	  If you don't know what to do here, say "Y".
88
89config ERRATA_THEAD_PMU
90	bool "Apply T-Head PMU errata"
91	depends on ERRATA_THEAD && RISCV_PMU_SBI
92	default y
93	help
94	  The T-Head C9xx cores implement a PMU overflow extension very
95	  similar to the core SSCOFPMF extension.
96
97	  This will apply the overflow errata to handle the non-standard
98	  behaviour via the regular SBI PMU driver and interface.
99
100	  If you don't know what to do here, say "Y".
101
102endmenu # "CPU errata selection"
103