1menu "CPU errata selection" 2 3config ERRATA_SIFIVE 4 bool "SiFive errata" 5 depends on RISCV_ALTERNATIVE 6 help 7 All SiFive errata Kconfig depend on this Kconfig. Disabling 8 this Kconfig will disable all SiFive errata. Please say "Y" 9 here if your platform uses SiFive CPU cores. 10 11 Otherwise, please say "N" here to avoid unnecessary overhead. 12 13config ERRATA_SIFIVE_CIP_453 14 bool "Apply SiFive errata CIP-453" 15 depends on ERRATA_SIFIVE && 64BIT 16 default y 17 help 18 This will apply the SiFive CIP-453 errata to add sign extension 19 to the $badaddr when exception type is instruction page fault 20 and instruction access fault. 21 22 If you don't know what to do here, say "Y". 23 24config ERRATA_SIFIVE_CIP_1200 25 bool "Apply SiFive errata CIP-1200" 26 depends on ERRATA_SIFIVE && 64BIT 27 default y 28 help 29 This will apply the SiFive CIP-1200 errata to repalce all 30 "sfence.vma addr" with "sfence.vma" to ensure that the addr 31 has been flushed from TLB. 32 33 If you don't know what to do here, say "Y". 34 35config ERRATA_THEAD 36 bool "T-HEAD errata" 37 depends on RISCV_ALTERNATIVE 38 help 39 All T-HEAD errata Kconfig depend on this Kconfig. Disabling 40 this Kconfig will disable all T-HEAD errata. Please say "Y" 41 here if your platform uses T-HEAD CPU cores. 42 43 Otherwise, please say "N" here to avoid unnecessary overhead. 44 45config ERRATA_THEAD_PBMT 46 bool "Apply T-Head memory type errata" 47 depends on ERRATA_THEAD && 64BIT && MMU 48 select RISCV_ALTERNATIVE_EARLY 49 default y 50 help 51 This will apply the memory type errata to handle the non-standard 52 memory type bits in page-table-entries on T-Head SoCs. 53 54 If you don't know what to do here, say "Y". 55 56config ERRATA_THEAD_CMO 57 bool "Apply T-Head cache management errata" 58 depends on ERRATA_THEAD && MMU 59 select RISCV_DMA_NONCOHERENT 60 default y 61 help 62 This will apply the cache management errata to handle the 63 non-standard handling on non-coherent operations on T-Head SoCs. 64 65 If you don't know what to do here, say "Y". 66 67config ERRATA_THEAD_PMU 68 bool "Apply T-Head PMU errata" 69 depends on ERRATA_THEAD && RISCV_PMU_SBI 70 default y 71 help 72 The T-Head C9xx cores implement a PMU overflow extension very 73 similar to the core SSCOFPMF extension. 74 75 This will apply the overflow errata to handle the non-standard 76 behaviour via the regular SBI PMU driver and interface. 77 78 If you don't know what to do here, say "Y". 79 80endmenu # "CPU errata selection" 81