1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2016,2017 IBM Corporation. 4 */ 5 6 #define pr_fmt(fmt) "xive: " fmt 7 8 #include <linux/types.h> 9 #include <linux/irq.h> 10 #include <linux/smp.h> 11 #include <linux/interrupt.h> 12 #include <linux/init.h> 13 #include <linux/of.h> 14 #include <linux/of_address.h> 15 #include <linux/of_fdt.h> 16 #include <linux/slab.h> 17 #include <linux/spinlock.h> 18 #include <linux/cpumask.h> 19 #include <linux/mm.h> 20 #include <linux/delay.h> 21 #include <linux/libfdt.h> 22 23 #include <asm/machdep.h> 24 #include <asm/prom.h> 25 #include <asm/io.h> 26 #include <asm/smp.h> 27 #include <asm/irq.h> 28 #include <asm/errno.h> 29 #include <asm/xive.h> 30 #include <asm/xive-regs.h> 31 #include <asm/hvcall.h> 32 #include <asm/svm.h> 33 #include <asm/ultravisor.h> 34 35 #include "xive-internal.h" 36 37 static u32 xive_queue_shift; 38 39 struct xive_irq_bitmap { 40 unsigned long *bitmap; 41 unsigned int base; 42 unsigned int count; 43 spinlock_t lock; 44 struct list_head list; 45 }; 46 47 static LIST_HEAD(xive_irq_bitmaps); 48 49 static int __init xive_irq_bitmap_add(int base, int count) 50 { 51 struct xive_irq_bitmap *xibm; 52 53 xibm = kzalloc(sizeof(*xibm), GFP_KERNEL); 54 if (!xibm) 55 return -ENOMEM; 56 57 spin_lock_init(&xibm->lock); 58 xibm->base = base; 59 xibm->count = count; 60 xibm->bitmap = kzalloc(xibm->count, GFP_KERNEL); 61 if (!xibm->bitmap) { 62 kfree(xibm); 63 return -ENOMEM; 64 } 65 list_add(&xibm->list, &xive_irq_bitmaps); 66 67 pr_info("Using IRQ range [%x-%x]", xibm->base, 68 xibm->base + xibm->count - 1); 69 return 0; 70 } 71 72 static void xive_irq_bitmap_remove_all(void) 73 { 74 struct xive_irq_bitmap *xibm, *tmp; 75 76 list_for_each_entry_safe(xibm, tmp, &xive_irq_bitmaps, list) { 77 list_del(&xibm->list); 78 kfree(xibm->bitmap); 79 kfree(xibm); 80 } 81 } 82 83 static int __xive_irq_bitmap_alloc(struct xive_irq_bitmap *xibm) 84 { 85 int irq; 86 87 irq = find_first_zero_bit(xibm->bitmap, xibm->count); 88 if (irq != xibm->count) { 89 set_bit(irq, xibm->bitmap); 90 irq += xibm->base; 91 } else { 92 irq = -ENOMEM; 93 } 94 95 return irq; 96 } 97 98 static int xive_irq_bitmap_alloc(void) 99 { 100 struct xive_irq_bitmap *xibm; 101 unsigned long flags; 102 int irq = -ENOENT; 103 104 list_for_each_entry(xibm, &xive_irq_bitmaps, list) { 105 spin_lock_irqsave(&xibm->lock, flags); 106 irq = __xive_irq_bitmap_alloc(xibm); 107 spin_unlock_irqrestore(&xibm->lock, flags); 108 if (irq >= 0) 109 break; 110 } 111 return irq; 112 } 113 114 static void xive_irq_bitmap_free(int irq) 115 { 116 unsigned long flags; 117 struct xive_irq_bitmap *xibm; 118 119 list_for_each_entry(xibm, &xive_irq_bitmaps, list) { 120 if ((irq >= xibm->base) && (irq < xibm->base + xibm->count)) { 121 spin_lock_irqsave(&xibm->lock, flags); 122 clear_bit(irq - xibm->base, xibm->bitmap); 123 spin_unlock_irqrestore(&xibm->lock, flags); 124 break; 125 } 126 } 127 } 128 129 130 /* Based on the similar routines in RTAS */ 131 static unsigned int plpar_busy_delay_time(long rc) 132 { 133 unsigned int ms = 0; 134 135 if (H_IS_LONG_BUSY(rc)) { 136 ms = get_longbusy_msecs(rc); 137 } else if (rc == H_BUSY) { 138 ms = 10; /* seems appropriate for XIVE hcalls */ 139 } 140 141 return ms; 142 } 143 144 static unsigned int plpar_busy_delay(int rc) 145 { 146 unsigned int ms; 147 148 ms = plpar_busy_delay_time(rc); 149 if (ms) 150 mdelay(ms); 151 152 return ms; 153 } 154 155 /* 156 * Note: this call has a partition wide scope and can take a while to 157 * complete. If it returns H_LONG_BUSY_* it should be retried 158 * periodically. 159 */ 160 static long plpar_int_reset(unsigned long flags) 161 { 162 long rc; 163 164 do { 165 rc = plpar_hcall_norets(H_INT_RESET, flags); 166 } while (plpar_busy_delay(rc)); 167 168 if (rc) 169 pr_err("H_INT_RESET failed %ld\n", rc); 170 171 return rc; 172 } 173 174 static long plpar_int_get_source_info(unsigned long flags, 175 unsigned long lisn, 176 unsigned long *src_flags, 177 unsigned long *eoi_page, 178 unsigned long *trig_page, 179 unsigned long *esb_shift) 180 { 181 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 182 long rc; 183 184 do { 185 rc = plpar_hcall(H_INT_GET_SOURCE_INFO, retbuf, flags, lisn); 186 } while (plpar_busy_delay(rc)); 187 188 if (rc) { 189 pr_err("H_INT_GET_SOURCE_INFO lisn=0x%lx failed %ld\n", lisn, rc); 190 return rc; 191 } 192 193 *src_flags = retbuf[0]; 194 *eoi_page = retbuf[1]; 195 *trig_page = retbuf[2]; 196 *esb_shift = retbuf[3]; 197 198 pr_debug("H_INT_GET_SOURCE_INFO lisn=0x%lx flags=0x%lx eoi=0x%lx trig=0x%lx shift=0x%lx\n", 199 lisn, retbuf[0], retbuf[1], retbuf[2], retbuf[3]); 200 201 return 0; 202 } 203 204 #define XIVE_SRC_SET_EISN (1ull << (63 - 62)) 205 #define XIVE_SRC_MASK (1ull << (63 - 63)) /* unused */ 206 207 static long plpar_int_set_source_config(unsigned long flags, 208 unsigned long lisn, 209 unsigned long target, 210 unsigned long prio, 211 unsigned long sw_irq) 212 { 213 long rc; 214 215 216 pr_debug("H_INT_SET_SOURCE_CONFIG flags=0x%lx lisn=0x%lx target=%ld prio=%ld sw_irq=%ld\n", 217 flags, lisn, target, prio, sw_irq); 218 219 220 do { 221 rc = plpar_hcall_norets(H_INT_SET_SOURCE_CONFIG, flags, lisn, 222 target, prio, sw_irq); 223 } while (plpar_busy_delay(rc)); 224 225 if (rc) { 226 pr_err("H_INT_SET_SOURCE_CONFIG lisn=0x%lx target=%ld prio=%ld failed %ld\n", 227 lisn, target, prio, rc); 228 return rc; 229 } 230 231 return 0; 232 } 233 234 static long plpar_int_get_source_config(unsigned long flags, 235 unsigned long lisn, 236 unsigned long *target, 237 unsigned long *prio, 238 unsigned long *sw_irq) 239 { 240 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 241 long rc; 242 243 pr_debug("H_INT_GET_SOURCE_CONFIG flags=0x%lx lisn=0x%lx\n", flags, lisn); 244 245 do { 246 rc = plpar_hcall(H_INT_GET_SOURCE_CONFIG, retbuf, flags, lisn, 247 target, prio, sw_irq); 248 } while (plpar_busy_delay(rc)); 249 250 if (rc) { 251 pr_err("H_INT_GET_SOURCE_CONFIG lisn=0x%lx failed %ld\n", 252 lisn, rc); 253 return rc; 254 } 255 256 *target = retbuf[0]; 257 *prio = retbuf[1]; 258 *sw_irq = retbuf[2]; 259 260 pr_debug("H_INT_GET_SOURCE_CONFIG target=%ld prio=%ld sw_irq=%ld\n", 261 retbuf[0], retbuf[1], retbuf[2]); 262 263 return 0; 264 } 265 266 static long plpar_int_get_queue_info(unsigned long flags, 267 unsigned long target, 268 unsigned long priority, 269 unsigned long *esn_page, 270 unsigned long *esn_size) 271 { 272 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 273 long rc; 274 275 do { 276 rc = plpar_hcall(H_INT_GET_QUEUE_INFO, retbuf, flags, target, 277 priority); 278 } while (plpar_busy_delay(rc)); 279 280 if (rc) { 281 pr_err("H_INT_GET_QUEUE_INFO cpu=%ld prio=%ld failed %ld\n", 282 target, priority, rc); 283 return rc; 284 } 285 286 *esn_page = retbuf[0]; 287 *esn_size = retbuf[1]; 288 289 pr_debug("H_INT_GET_QUEUE_INFO cpu=%ld prio=%ld page=0x%lx size=0x%lx\n", 290 target, priority, retbuf[0], retbuf[1]); 291 292 return 0; 293 } 294 295 #define XIVE_EQ_ALWAYS_NOTIFY (1ull << (63 - 63)) 296 297 static long plpar_int_set_queue_config(unsigned long flags, 298 unsigned long target, 299 unsigned long priority, 300 unsigned long qpage, 301 unsigned long qsize) 302 { 303 long rc; 304 305 pr_debug("H_INT_SET_QUEUE_CONFIG flags=0x%lx target=%ld priority=0x%lx qpage=0x%lx qsize=0x%lx\n", 306 flags, target, priority, qpage, qsize); 307 308 do { 309 rc = plpar_hcall_norets(H_INT_SET_QUEUE_CONFIG, flags, target, 310 priority, qpage, qsize); 311 } while (plpar_busy_delay(rc)); 312 313 if (rc) { 314 pr_err("H_INT_SET_QUEUE_CONFIG cpu=%ld prio=%ld qpage=0x%lx returned %ld\n", 315 target, priority, qpage, rc); 316 return rc; 317 } 318 319 return 0; 320 } 321 322 static long plpar_int_sync(unsigned long flags, unsigned long lisn) 323 { 324 long rc; 325 326 do { 327 rc = plpar_hcall_norets(H_INT_SYNC, flags, lisn); 328 } while (plpar_busy_delay(rc)); 329 330 if (rc) { 331 pr_err("H_INT_SYNC lisn=0x%lx returned %ld\n", lisn, rc); 332 return rc; 333 } 334 335 return 0; 336 } 337 338 #define XIVE_ESB_FLAG_STORE (1ull << (63 - 63)) 339 340 static long plpar_int_esb(unsigned long flags, 341 unsigned long lisn, 342 unsigned long offset, 343 unsigned long in_data, 344 unsigned long *out_data) 345 { 346 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 347 long rc; 348 349 pr_debug("H_INT_ESB flags=0x%lx lisn=0x%lx offset=0x%lx in=0x%lx\n", 350 flags, lisn, offset, in_data); 351 352 do { 353 rc = plpar_hcall(H_INT_ESB, retbuf, flags, lisn, offset, 354 in_data); 355 } while (plpar_busy_delay(rc)); 356 357 if (rc) { 358 pr_err("H_INT_ESB lisn=0x%lx offset=0x%lx returned %ld\n", 359 lisn, offset, rc); 360 return rc; 361 } 362 363 *out_data = retbuf[0]; 364 365 return 0; 366 } 367 368 static u64 xive_spapr_esb_rw(u32 lisn, u32 offset, u64 data, bool write) 369 { 370 unsigned long read_data; 371 long rc; 372 373 rc = plpar_int_esb(write ? XIVE_ESB_FLAG_STORE : 0, 374 lisn, offset, data, &read_data); 375 if (rc) 376 return -1; 377 378 return write ? 0 : read_data; 379 } 380 381 #define XIVE_SRC_H_INT_ESB (1ull << (63 - 60)) 382 #define XIVE_SRC_LSI (1ull << (63 - 61)) 383 #define XIVE_SRC_TRIGGER (1ull << (63 - 62)) 384 #define XIVE_SRC_STORE_EOI (1ull << (63 - 63)) 385 386 static int xive_spapr_populate_irq_data(u32 hw_irq, struct xive_irq_data *data) 387 { 388 long rc; 389 unsigned long flags; 390 unsigned long eoi_page; 391 unsigned long trig_page; 392 unsigned long esb_shift; 393 394 memset(data, 0, sizeof(*data)); 395 396 rc = plpar_int_get_source_info(0, hw_irq, &flags, &eoi_page, &trig_page, 397 &esb_shift); 398 if (rc) 399 return -EINVAL; 400 401 if (flags & XIVE_SRC_H_INT_ESB) 402 data->flags |= XIVE_IRQ_FLAG_H_INT_ESB; 403 if (flags & XIVE_SRC_STORE_EOI) 404 data->flags |= XIVE_IRQ_FLAG_STORE_EOI; 405 if (flags & XIVE_SRC_LSI) 406 data->flags |= XIVE_IRQ_FLAG_LSI; 407 data->eoi_page = eoi_page; 408 data->esb_shift = esb_shift; 409 data->trig_page = trig_page; 410 411 data->hw_irq = hw_irq; 412 413 /* 414 * No chip-id for the sPAPR backend. This has an impact how we 415 * pick a target. See xive_pick_irq_target(). 416 */ 417 data->src_chip = XIVE_INVALID_CHIP_ID; 418 419 /* 420 * When the H_INT_ESB flag is set, the H_INT_ESB hcall should 421 * be used for interrupt management. Skip the remapping of the 422 * ESB pages which are not available. 423 */ 424 if (data->flags & XIVE_IRQ_FLAG_H_INT_ESB) 425 return 0; 426 427 data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift); 428 if (!data->eoi_mmio) { 429 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq); 430 return -ENOMEM; 431 } 432 433 /* Full function page supports trigger */ 434 if (flags & XIVE_SRC_TRIGGER) { 435 data->trig_mmio = data->eoi_mmio; 436 return 0; 437 } 438 439 data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift); 440 if (!data->trig_mmio) { 441 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq); 442 return -ENOMEM; 443 } 444 return 0; 445 } 446 447 static int xive_spapr_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq) 448 { 449 long rc; 450 451 rc = plpar_int_set_source_config(XIVE_SRC_SET_EISN, hw_irq, target, 452 prio, sw_irq); 453 454 return rc == 0 ? 0 : -ENXIO; 455 } 456 457 static int xive_spapr_get_irq_config(u32 hw_irq, u32 *target, u8 *prio, 458 u32 *sw_irq) 459 { 460 long rc; 461 unsigned long h_target; 462 unsigned long h_prio; 463 unsigned long h_sw_irq; 464 465 rc = plpar_int_get_source_config(0, hw_irq, &h_target, &h_prio, 466 &h_sw_irq); 467 468 *target = h_target; 469 *prio = h_prio; 470 *sw_irq = h_sw_irq; 471 472 return rc == 0 ? 0 : -ENXIO; 473 } 474 475 /* This can be called multiple time to change a queue configuration */ 476 static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio, 477 __be32 *qpage, u32 order) 478 { 479 s64 rc = 0; 480 unsigned long esn_page; 481 unsigned long esn_size; 482 u64 flags, qpage_phys; 483 484 /* If there's an actual queue page, clean it */ 485 if (order) { 486 if (WARN_ON(!qpage)) 487 return -EINVAL; 488 qpage_phys = __pa(qpage); 489 } else { 490 qpage_phys = 0; 491 } 492 493 /* Initialize the rest of the fields */ 494 q->msk = order ? ((1u << (order - 2)) - 1) : 0; 495 q->idx = 0; 496 q->toggle = 0; 497 498 rc = plpar_int_get_queue_info(0, target, prio, &esn_page, &esn_size); 499 if (rc) { 500 pr_err("Error %lld getting queue info CPU %d prio %d\n", rc, 501 target, prio); 502 rc = -EIO; 503 goto fail; 504 } 505 506 /* TODO: add support for the notification page */ 507 q->eoi_phys = esn_page; 508 509 /* Default is to always notify */ 510 flags = XIVE_EQ_ALWAYS_NOTIFY; 511 512 /* Configure and enable the queue in HW */ 513 rc = plpar_int_set_queue_config(flags, target, prio, qpage_phys, order); 514 if (rc) { 515 pr_err("Error %lld setting queue for CPU %d prio %d\n", rc, 516 target, prio); 517 rc = -EIO; 518 } else { 519 q->qpage = qpage; 520 if (is_secure_guest()) 521 uv_share_page(PHYS_PFN(qpage_phys), 522 1 << xive_alloc_order(order)); 523 } 524 fail: 525 return rc; 526 } 527 528 static int xive_spapr_setup_queue(unsigned int cpu, struct xive_cpu *xc, 529 u8 prio) 530 { 531 struct xive_q *q = &xc->queue[prio]; 532 __be32 *qpage; 533 534 qpage = xive_queue_page_alloc(cpu, xive_queue_shift); 535 if (IS_ERR(qpage)) 536 return PTR_ERR(qpage); 537 538 return xive_spapr_configure_queue(get_hard_smp_processor_id(cpu), 539 q, prio, qpage, xive_queue_shift); 540 } 541 542 static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, 543 u8 prio) 544 { 545 struct xive_q *q = &xc->queue[prio]; 546 unsigned int alloc_order; 547 long rc; 548 int hw_cpu = get_hard_smp_processor_id(cpu); 549 550 rc = plpar_int_set_queue_config(0, hw_cpu, prio, 0, 0); 551 if (rc) 552 pr_err("Error %ld setting queue for CPU %d prio %d\n", rc, 553 hw_cpu, prio); 554 555 alloc_order = xive_alloc_order(xive_queue_shift); 556 if (is_secure_guest()) 557 uv_unshare_page(PHYS_PFN(__pa(q->qpage)), 1 << alloc_order); 558 free_pages((unsigned long)q->qpage, alloc_order); 559 q->qpage = NULL; 560 } 561 562 static bool xive_spapr_match(struct device_node *node) 563 { 564 /* Ignore cascaded controllers for the moment */ 565 return true; 566 } 567 568 #ifdef CONFIG_SMP 569 static int xive_spapr_get_ipi(unsigned int cpu, struct xive_cpu *xc) 570 { 571 int irq = xive_irq_bitmap_alloc(); 572 573 if (irq < 0) { 574 pr_err("Failed to allocate IPI on CPU %d\n", cpu); 575 return -ENXIO; 576 } 577 578 xc->hw_ipi = irq; 579 return 0; 580 } 581 582 static void xive_spapr_put_ipi(unsigned int cpu, struct xive_cpu *xc) 583 { 584 if (xc->hw_ipi == XIVE_BAD_IRQ) 585 return; 586 587 xive_irq_bitmap_free(xc->hw_ipi); 588 xc->hw_ipi = XIVE_BAD_IRQ; 589 } 590 #endif /* CONFIG_SMP */ 591 592 static void xive_spapr_shutdown(void) 593 { 594 plpar_int_reset(0); 595 } 596 597 /* 598 * Perform an "ack" cycle on the current thread. Grab the pending 599 * active priorities and update the CPPR to the most favored one. 600 */ 601 static void xive_spapr_update_pending(struct xive_cpu *xc) 602 { 603 u8 nsr, cppr; 604 u16 ack; 605 606 /* 607 * Perform the "Acknowledge O/S to Register" cycle. 608 * 609 * Let's speedup the access to the TIMA using the raw I/O 610 * accessor as we don't need the synchronisation routine of 611 * the higher level ones 612 */ 613 ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_OS_REG)); 614 615 /* Synchronize subsequent queue accesses */ 616 mb(); 617 618 /* 619 * Grab the CPPR and the "NSR" field which indicates the source 620 * of the interrupt (if any) 621 */ 622 cppr = ack & 0xff; 623 nsr = ack >> 8; 624 625 if (nsr & TM_QW1_NSR_EO) { 626 if (cppr == 0xff) 627 return; 628 /* Mark the priority pending */ 629 xc->pending_prio |= 1 << cppr; 630 631 /* 632 * A new interrupt should never have a CPPR less favored 633 * than our current one. 634 */ 635 if (cppr >= xc->cppr) 636 pr_err("CPU %d odd ack CPPR, got %d at %d\n", 637 smp_processor_id(), cppr, xc->cppr); 638 639 /* Update our idea of what the CPPR is */ 640 xc->cppr = cppr; 641 } 642 } 643 644 static void xive_spapr_setup_cpu(unsigned int cpu, struct xive_cpu *xc) 645 { 646 /* Only some debug on the TIMA settings */ 647 pr_debug("(HW value: %08x %08x %08x)\n", 648 in_be32(xive_tima + TM_QW1_OS + TM_WORD0), 649 in_be32(xive_tima + TM_QW1_OS + TM_WORD1), 650 in_be32(xive_tima + TM_QW1_OS + TM_WORD2)); 651 } 652 653 static void xive_spapr_teardown_cpu(unsigned int cpu, struct xive_cpu *xc) 654 { 655 /* Nothing to do */; 656 } 657 658 static void xive_spapr_sync_source(u32 hw_irq) 659 { 660 /* Specs are unclear on what this is doing */ 661 plpar_int_sync(0, hw_irq); 662 } 663 664 static int xive_spapr_debug_show(struct seq_file *m, void *private) 665 { 666 struct xive_irq_bitmap *xibm; 667 char *buf = kmalloc(PAGE_SIZE, GFP_KERNEL); 668 669 if (!buf) 670 return -ENOMEM; 671 672 list_for_each_entry(xibm, &xive_irq_bitmaps, list) { 673 memset(buf, 0, PAGE_SIZE); 674 bitmap_print_to_pagebuf(true, buf, xibm->bitmap, xibm->count); 675 seq_printf(m, "bitmap #%d: %s", xibm->count, buf); 676 } 677 kfree(buf); 678 679 return 0; 680 } 681 682 static const struct xive_ops xive_spapr_ops = { 683 .populate_irq_data = xive_spapr_populate_irq_data, 684 .configure_irq = xive_spapr_configure_irq, 685 .get_irq_config = xive_spapr_get_irq_config, 686 .setup_queue = xive_spapr_setup_queue, 687 .cleanup_queue = xive_spapr_cleanup_queue, 688 .match = xive_spapr_match, 689 .shutdown = xive_spapr_shutdown, 690 .update_pending = xive_spapr_update_pending, 691 .setup_cpu = xive_spapr_setup_cpu, 692 .teardown_cpu = xive_spapr_teardown_cpu, 693 .sync_source = xive_spapr_sync_source, 694 .esb_rw = xive_spapr_esb_rw, 695 #ifdef CONFIG_SMP 696 .get_ipi = xive_spapr_get_ipi, 697 .put_ipi = xive_spapr_put_ipi, 698 .debug_show = xive_spapr_debug_show, 699 #endif /* CONFIG_SMP */ 700 .name = "spapr", 701 }; 702 703 /* 704 * get max priority from "/ibm,plat-res-int-priorities" 705 */ 706 static bool __init xive_get_max_prio(u8 *max_prio) 707 { 708 struct device_node *rootdn; 709 const __be32 *reg; 710 u32 len; 711 int prio, found; 712 713 rootdn = of_find_node_by_path("/"); 714 if (!rootdn) { 715 pr_err("not root node found !\n"); 716 return false; 717 } 718 719 reg = of_get_property(rootdn, "ibm,plat-res-int-priorities", &len); 720 if (!reg) { 721 pr_err("Failed to read 'ibm,plat-res-int-priorities' property\n"); 722 return false; 723 } 724 725 if (len % (2 * sizeof(u32)) != 0) { 726 pr_err("invalid 'ibm,plat-res-int-priorities' property\n"); 727 return false; 728 } 729 730 /* HW supports priorities in the range [0-7] and 0xFF is a 731 * wildcard priority used to mask. We scan the ranges reserved 732 * by the hypervisor to find the lowest priority we can use. 733 */ 734 found = 0xFF; 735 for (prio = 0; prio < 8; prio++) { 736 int reserved = 0; 737 int i; 738 739 for (i = 0; i < len / (2 * sizeof(u32)); i++) { 740 int base = be32_to_cpu(reg[2 * i]); 741 int range = be32_to_cpu(reg[2 * i + 1]); 742 743 if (prio >= base && prio < base + range) 744 reserved++; 745 } 746 747 if (!reserved) 748 found = prio; 749 } 750 751 if (found == 0xFF) { 752 pr_err("no valid priority found in 'ibm,plat-res-int-priorities'\n"); 753 return false; 754 } 755 756 *max_prio = found; 757 return true; 758 } 759 760 static const u8 *__init get_vec5_feature(unsigned int index) 761 { 762 unsigned long root, chosen; 763 int size; 764 const u8 *vec5; 765 766 root = of_get_flat_dt_root(); 767 chosen = of_get_flat_dt_subnode_by_name(root, "chosen"); 768 if (chosen == -FDT_ERR_NOTFOUND) 769 return NULL; 770 771 vec5 = of_get_flat_dt_prop(chosen, "ibm,architecture-vec-5", &size); 772 if (!vec5) 773 return NULL; 774 775 if (size <= index) 776 return NULL; 777 778 return vec5 + index; 779 } 780 781 static bool __init xive_spapr_disabled(void) 782 { 783 const u8 *vec5_xive; 784 785 vec5_xive = get_vec5_feature(OV5_INDX(OV5_XIVE_SUPPORT)); 786 if (vec5_xive) { 787 u8 val; 788 789 val = *vec5_xive & OV5_FEAT(OV5_XIVE_SUPPORT); 790 switch (val) { 791 case OV5_FEAT(OV5_XIVE_EITHER): 792 case OV5_FEAT(OV5_XIVE_LEGACY): 793 break; 794 case OV5_FEAT(OV5_XIVE_EXPLOIT): 795 /* Hypervisor only supports XIVE */ 796 if (xive_cmdline_disabled) 797 pr_warn("WARNING: Ignoring cmdline option xive=off\n"); 798 return false; 799 default: 800 pr_warn("%s: Unknown xive support option: 0x%x\n", 801 __func__, val); 802 break; 803 } 804 } 805 806 return xive_cmdline_disabled; 807 } 808 809 bool __init xive_spapr_init(void) 810 { 811 struct device_node *np; 812 struct resource r; 813 void __iomem *tima; 814 struct property *prop; 815 u8 max_prio; 816 u32 val; 817 u32 len; 818 const __be32 *reg; 819 int i, err; 820 821 if (xive_spapr_disabled()) 822 return false; 823 824 pr_devel("%s()\n", __func__); 825 np = of_find_compatible_node(NULL, NULL, "ibm,power-ivpe"); 826 if (!np) { 827 pr_devel("not found !\n"); 828 return false; 829 } 830 pr_devel("Found %s\n", np->full_name); 831 832 /* Resource 1 is the OS ring TIMA */ 833 if (of_address_to_resource(np, 1, &r)) { 834 pr_err("Failed to get thread mgmnt area resource\n"); 835 goto err_put; 836 } 837 tima = ioremap(r.start, resource_size(&r)); 838 if (!tima) { 839 pr_err("Failed to map thread mgmnt area\n"); 840 goto err_put; 841 } 842 843 if (!xive_get_max_prio(&max_prio)) 844 goto err_unmap; 845 846 /* Feed the IRQ number allocator with the ranges given in the DT */ 847 reg = of_get_property(np, "ibm,xive-lisn-ranges", &len); 848 if (!reg) { 849 pr_err("Failed to read 'ibm,xive-lisn-ranges' property\n"); 850 goto err_unmap; 851 } 852 853 if (len % (2 * sizeof(u32)) != 0) { 854 pr_err("invalid 'ibm,xive-lisn-ranges' property\n"); 855 goto err_unmap; 856 } 857 858 for (i = 0; i < len / (2 * sizeof(u32)); i++, reg += 2) { 859 err = xive_irq_bitmap_add(be32_to_cpu(reg[0]), 860 be32_to_cpu(reg[1])); 861 if (err < 0) 862 goto err_mem_free; 863 } 864 865 /* Iterate the EQ sizes and pick one */ 866 of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, reg, val) { 867 xive_queue_shift = val; 868 if (val == PAGE_SHIFT) 869 break; 870 } 871 872 /* Initialize XIVE core with our backend */ 873 if (!xive_core_init(np, &xive_spapr_ops, tima, TM_QW1_OS, max_prio)) 874 goto err_mem_free; 875 876 of_node_put(np); 877 pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10)); 878 return true; 879 880 err_mem_free: 881 xive_irq_bitmap_remove_all(); 882 err_unmap: 883 iounmap(tima); 884 err_put: 885 of_node_put(np); 886 return false; 887 } 888 889 machine_arch_initcall(pseries, xive_core_debug_init); 890