1 /* 2 * Copyright 2016,2017 IBM Corporation. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10 #define pr_fmt(fmt) "xive: " fmt 11 12 #include <linux/types.h> 13 #include <linux/irq.h> 14 #include <linux/smp.h> 15 #include <linux/interrupt.h> 16 #include <linux/init.h> 17 #include <linux/of.h> 18 #include <linux/slab.h> 19 #include <linux/spinlock.h> 20 #include <linux/cpumask.h> 21 #include <linux/mm.h> 22 #include <linux/delay.h> 23 24 #include <asm/prom.h> 25 #include <asm/io.h> 26 #include <asm/smp.h> 27 #include <asm/irq.h> 28 #include <asm/errno.h> 29 #include <asm/xive.h> 30 #include <asm/xive-regs.h> 31 #include <asm/hvcall.h> 32 33 #include "xive-internal.h" 34 35 static u32 xive_queue_shift; 36 37 struct xive_irq_bitmap { 38 unsigned long *bitmap; 39 unsigned int base; 40 unsigned int count; 41 spinlock_t lock; 42 struct list_head list; 43 }; 44 45 static LIST_HEAD(xive_irq_bitmaps); 46 47 static int xive_irq_bitmap_add(int base, int count) 48 { 49 struct xive_irq_bitmap *xibm; 50 51 xibm = kzalloc(sizeof(*xibm), GFP_ATOMIC); 52 if (!xibm) 53 return -ENOMEM; 54 55 spin_lock_init(&xibm->lock); 56 xibm->base = base; 57 xibm->count = count; 58 xibm->bitmap = kzalloc(xibm->count, GFP_KERNEL); 59 list_add(&xibm->list, &xive_irq_bitmaps); 60 61 pr_info("Using IRQ range [%x-%x]", xibm->base, 62 xibm->base + xibm->count - 1); 63 return 0; 64 } 65 66 static int __xive_irq_bitmap_alloc(struct xive_irq_bitmap *xibm) 67 { 68 int irq; 69 70 irq = find_first_zero_bit(xibm->bitmap, xibm->count); 71 if (irq != xibm->count) { 72 set_bit(irq, xibm->bitmap); 73 irq += xibm->base; 74 } else { 75 irq = -ENOMEM; 76 } 77 78 return irq; 79 } 80 81 static int xive_irq_bitmap_alloc(void) 82 { 83 struct xive_irq_bitmap *xibm; 84 unsigned long flags; 85 int irq = -ENOENT; 86 87 list_for_each_entry(xibm, &xive_irq_bitmaps, list) { 88 spin_lock_irqsave(&xibm->lock, flags); 89 irq = __xive_irq_bitmap_alloc(xibm); 90 spin_unlock_irqrestore(&xibm->lock, flags); 91 if (irq >= 0) 92 break; 93 } 94 return irq; 95 } 96 97 static void xive_irq_bitmap_free(int irq) 98 { 99 unsigned long flags; 100 struct xive_irq_bitmap *xibm; 101 102 list_for_each_entry(xibm, &xive_irq_bitmaps, list) { 103 if ((irq >= xibm->base) && (irq < xibm->base + xibm->count)) { 104 spin_lock_irqsave(&xibm->lock, flags); 105 clear_bit(irq - xibm->base, xibm->bitmap); 106 spin_unlock_irqrestore(&xibm->lock, flags); 107 break; 108 } 109 } 110 } 111 112 113 /* Based on the similar routines in RTAS */ 114 static unsigned int plpar_busy_delay_time(long rc) 115 { 116 unsigned int ms = 0; 117 118 if (H_IS_LONG_BUSY(rc)) { 119 ms = get_longbusy_msecs(rc); 120 } else if (rc == H_BUSY) { 121 ms = 10; /* seems appropriate for XIVE hcalls */ 122 } 123 124 return ms; 125 } 126 127 static unsigned int plpar_busy_delay(int rc) 128 { 129 unsigned int ms; 130 131 ms = plpar_busy_delay_time(rc); 132 if (ms) 133 mdelay(ms); 134 135 return ms; 136 } 137 138 /* 139 * Note: this call has a partition wide scope and can take a while to 140 * complete. If it returns H_LONG_BUSY_* it should be retried 141 * periodically. 142 */ 143 static long plpar_int_reset(unsigned long flags) 144 { 145 long rc; 146 147 do { 148 rc = plpar_hcall_norets(H_INT_RESET, flags); 149 } while (plpar_busy_delay(rc)); 150 151 if (rc) 152 pr_err("H_INT_RESET failed %ld\n", rc); 153 154 return rc; 155 } 156 157 static long plpar_int_get_source_info(unsigned long flags, 158 unsigned long lisn, 159 unsigned long *src_flags, 160 unsigned long *eoi_page, 161 unsigned long *trig_page, 162 unsigned long *esb_shift) 163 { 164 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 165 long rc; 166 167 do { 168 rc = plpar_hcall(H_INT_GET_SOURCE_INFO, retbuf, flags, lisn); 169 } while (plpar_busy_delay(rc)); 170 171 if (rc) { 172 pr_err("H_INT_GET_SOURCE_INFO lisn=%ld failed %ld\n", lisn, rc); 173 return rc; 174 } 175 176 *src_flags = retbuf[0]; 177 *eoi_page = retbuf[1]; 178 *trig_page = retbuf[2]; 179 *esb_shift = retbuf[3]; 180 181 pr_devel("H_INT_GET_SOURCE_INFO flags=%lx eoi=%lx trig=%lx shift=%lx\n", 182 retbuf[0], retbuf[1], retbuf[2], retbuf[3]); 183 184 return 0; 185 } 186 187 #define XIVE_SRC_SET_EISN (1ull << (63 - 62)) 188 #define XIVE_SRC_MASK (1ull << (63 - 63)) /* unused */ 189 190 static long plpar_int_set_source_config(unsigned long flags, 191 unsigned long lisn, 192 unsigned long target, 193 unsigned long prio, 194 unsigned long sw_irq) 195 { 196 long rc; 197 198 199 pr_devel("H_INT_SET_SOURCE_CONFIG flags=%lx lisn=%lx target=%lx prio=%lx sw_irq=%lx\n", 200 flags, lisn, target, prio, sw_irq); 201 202 203 do { 204 rc = plpar_hcall_norets(H_INT_SET_SOURCE_CONFIG, flags, lisn, 205 target, prio, sw_irq); 206 } while (plpar_busy_delay(rc)); 207 208 if (rc) { 209 pr_err("H_INT_SET_SOURCE_CONFIG lisn=%ld target=%lx prio=%lx failed %ld\n", 210 lisn, target, prio, rc); 211 return rc; 212 } 213 214 return 0; 215 } 216 217 static long plpar_int_get_queue_info(unsigned long flags, 218 unsigned long target, 219 unsigned long priority, 220 unsigned long *esn_page, 221 unsigned long *esn_size) 222 { 223 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 224 long rc; 225 226 do { 227 rc = plpar_hcall(H_INT_GET_QUEUE_INFO, retbuf, flags, target, 228 priority); 229 } while (plpar_busy_delay(rc)); 230 231 if (rc) { 232 pr_err("H_INT_GET_QUEUE_INFO cpu=%ld prio=%ld failed %ld\n", 233 target, priority, rc); 234 return rc; 235 } 236 237 *esn_page = retbuf[0]; 238 *esn_size = retbuf[1]; 239 240 pr_devel("H_INT_GET_QUEUE_INFO page=%lx size=%lx\n", 241 retbuf[0], retbuf[1]); 242 243 return 0; 244 } 245 246 #define XIVE_EQ_ALWAYS_NOTIFY (1ull << (63 - 63)) 247 248 static long plpar_int_set_queue_config(unsigned long flags, 249 unsigned long target, 250 unsigned long priority, 251 unsigned long qpage, 252 unsigned long qsize) 253 { 254 long rc; 255 256 pr_devel("H_INT_SET_QUEUE_CONFIG flags=%lx target=%lx priority=%lx qpage=%lx qsize=%lx\n", 257 flags, target, priority, qpage, qsize); 258 259 do { 260 rc = plpar_hcall_norets(H_INT_SET_QUEUE_CONFIG, flags, target, 261 priority, qpage, qsize); 262 } while (plpar_busy_delay(rc)); 263 264 if (rc) { 265 pr_err("H_INT_SET_QUEUE_CONFIG cpu=%ld prio=%ld qpage=%lx returned %ld\n", 266 target, priority, qpage, rc); 267 return rc; 268 } 269 270 return 0; 271 } 272 273 static long plpar_int_sync(unsigned long flags, unsigned long lisn) 274 { 275 long rc; 276 277 do { 278 rc = plpar_hcall_norets(H_INT_SYNC, flags, lisn); 279 } while (plpar_busy_delay(rc)); 280 281 if (rc) { 282 pr_err("H_INT_SYNC lisn=%ld returned %ld\n", lisn, rc); 283 return rc; 284 } 285 286 return 0; 287 } 288 289 #define XIVE_ESB_FLAG_STORE (1ull << (63 - 63)) 290 291 static long plpar_int_esb(unsigned long flags, 292 unsigned long lisn, 293 unsigned long offset, 294 unsigned long in_data, 295 unsigned long *out_data) 296 { 297 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 298 long rc; 299 300 pr_devel("H_INT_ESB flags=%lx lisn=%lx offset=%lx in=%lx\n", 301 flags, lisn, offset, in_data); 302 303 do { 304 rc = plpar_hcall(H_INT_ESB, retbuf, flags, lisn, offset, 305 in_data); 306 } while (plpar_busy_delay(rc)); 307 308 if (rc) { 309 pr_err("H_INT_ESB lisn=%ld offset=%ld returned %ld\n", 310 lisn, offset, rc); 311 return rc; 312 } 313 314 *out_data = retbuf[0]; 315 316 return 0; 317 } 318 319 static u64 xive_spapr_esb_rw(u32 lisn, u32 offset, u64 data, bool write) 320 { 321 unsigned long read_data; 322 long rc; 323 324 rc = plpar_int_esb(write ? XIVE_ESB_FLAG_STORE : 0, 325 lisn, offset, data, &read_data); 326 if (rc) 327 return -1; 328 329 return write ? 0 : read_data; 330 } 331 332 #define XIVE_SRC_H_INT_ESB (1ull << (63 - 60)) 333 #define XIVE_SRC_LSI (1ull << (63 - 61)) 334 #define XIVE_SRC_TRIGGER (1ull << (63 - 62)) 335 #define XIVE_SRC_STORE_EOI (1ull << (63 - 63)) 336 337 static int xive_spapr_populate_irq_data(u32 hw_irq, struct xive_irq_data *data) 338 { 339 long rc; 340 unsigned long flags; 341 unsigned long eoi_page; 342 unsigned long trig_page; 343 unsigned long esb_shift; 344 345 memset(data, 0, sizeof(*data)); 346 347 rc = plpar_int_get_source_info(0, hw_irq, &flags, &eoi_page, &trig_page, 348 &esb_shift); 349 if (rc) 350 return -EINVAL; 351 352 if (flags & XIVE_SRC_H_INT_ESB) 353 data->flags |= XIVE_IRQ_FLAG_H_INT_ESB; 354 if (flags & XIVE_SRC_STORE_EOI) 355 data->flags |= XIVE_IRQ_FLAG_STORE_EOI; 356 if (flags & XIVE_SRC_LSI) 357 data->flags |= XIVE_IRQ_FLAG_LSI; 358 data->eoi_page = eoi_page; 359 data->esb_shift = esb_shift; 360 data->trig_page = trig_page; 361 362 /* 363 * No chip-id for the sPAPR backend. This has an impact how we 364 * pick a target. See xive_pick_irq_target(). 365 */ 366 data->src_chip = XIVE_INVALID_CHIP_ID; 367 368 data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift); 369 if (!data->eoi_mmio) { 370 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq); 371 return -ENOMEM; 372 } 373 374 data->hw_irq = hw_irq; 375 376 /* Full function page supports trigger */ 377 if (flags & XIVE_SRC_TRIGGER) { 378 data->trig_mmio = data->eoi_mmio; 379 return 0; 380 } 381 382 data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift); 383 if (!data->trig_mmio) { 384 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq); 385 return -ENOMEM; 386 } 387 return 0; 388 } 389 390 static int xive_spapr_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq) 391 { 392 long rc; 393 394 rc = plpar_int_set_source_config(XIVE_SRC_SET_EISN, hw_irq, target, 395 prio, sw_irq); 396 397 return rc == 0 ? 0 : -ENXIO; 398 } 399 400 /* This can be called multiple time to change a queue configuration */ 401 static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio, 402 __be32 *qpage, u32 order) 403 { 404 s64 rc = 0; 405 unsigned long esn_page; 406 unsigned long esn_size; 407 u64 flags, qpage_phys; 408 409 /* If there's an actual queue page, clean it */ 410 if (order) { 411 if (WARN_ON(!qpage)) 412 return -EINVAL; 413 qpage_phys = __pa(qpage); 414 } else { 415 qpage_phys = 0; 416 } 417 418 /* Initialize the rest of the fields */ 419 q->msk = order ? ((1u << (order - 2)) - 1) : 0; 420 q->idx = 0; 421 q->toggle = 0; 422 423 rc = plpar_int_get_queue_info(0, target, prio, &esn_page, &esn_size); 424 if (rc) { 425 pr_err("Error %lld getting queue info CPU %d prio %d\n", rc, 426 target, prio); 427 rc = -EIO; 428 goto fail; 429 } 430 431 /* TODO: add support for the notification page */ 432 q->eoi_phys = esn_page; 433 434 /* Default is to always notify */ 435 flags = XIVE_EQ_ALWAYS_NOTIFY; 436 437 /* Configure and enable the queue in HW */ 438 rc = plpar_int_set_queue_config(flags, target, prio, qpage_phys, order); 439 if (rc) { 440 pr_err("Error %lld setting queue for CPU %d prio %d\n", rc, 441 target, prio); 442 rc = -EIO; 443 } else { 444 q->qpage = qpage; 445 } 446 fail: 447 return rc; 448 } 449 450 static int xive_spapr_setup_queue(unsigned int cpu, struct xive_cpu *xc, 451 u8 prio) 452 { 453 struct xive_q *q = &xc->queue[prio]; 454 __be32 *qpage; 455 456 qpage = xive_queue_page_alloc(cpu, xive_queue_shift); 457 if (IS_ERR(qpage)) 458 return PTR_ERR(qpage); 459 460 return xive_spapr_configure_queue(get_hard_smp_processor_id(cpu), 461 q, prio, qpage, xive_queue_shift); 462 } 463 464 static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, 465 u8 prio) 466 { 467 struct xive_q *q = &xc->queue[prio]; 468 unsigned int alloc_order; 469 long rc; 470 int hw_cpu = get_hard_smp_processor_id(cpu); 471 472 rc = plpar_int_set_queue_config(0, hw_cpu, prio, 0, 0); 473 if (rc) 474 pr_err("Error %ld setting queue for CPU %d prio %d\n", rc, 475 hw_cpu, prio); 476 477 alloc_order = xive_alloc_order(xive_queue_shift); 478 free_pages((unsigned long)q->qpage, alloc_order); 479 q->qpage = NULL; 480 } 481 482 static bool xive_spapr_match(struct device_node *node) 483 { 484 /* Ignore cascaded controllers for the moment */ 485 return 1; 486 } 487 488 #ifdef CONFIG_SMP 489 static int xive_spapr_get_ipi(unsigned int cpu, struct xive_cpu *xc) 490 { 491 int irq = xive_irq_bitmap_alloc(); 492 493 if (irq < 0) { 494 pr_err("Failed to allocate IPI on CPU %d\n", cpu); 495 return -ENXIO; 496 } 497 498 xc->hw_ipi = irq; 499 return 0; 500 } 501 502 static void xive_spapr_put_ipi(unsigned int cpu, struct xive_cpu *xc) 503 { 504 if (!xc->hw_ipi) 505 return; 506 507 xive_irq_bitmap_free(xc->hw_ipi); 508 xc->hw_ipi = 0; 509 } 510 #endif /* CONFIG_SMP */ 511 512 static void xive_spapr_shutdown(void) 513 { 514 plpar_int_reset(0); 515 } 516 517 /* 518 * Perform an "ack" cycle on the current thread. Grab the pending 519 * active priorities and update the CPPR to the most favored one. 520 */ 521 static void xive_spapr_update_pending(struct xive_cpu *xc) 522 { 523 u8 nsr, cppr; 524 u16 ack; 525 526 /* 527 * Perform the "Acknowledge O/S to Register" cycle. 528 * 529 * Let's speedup the access to the TIMA using the raw I/O 530 * accessor as we don't need the synchronisation routine of 531 * the higher level ones 532 */ 533 ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_OS_REG)); 534 535 /* Synchronize subsequent queue accesses */ 536 mb(); 537 538 /* 539 * Grab the CPPR and the "NSR" field which indicates the source 540 * of the interrupt (if any) 541 */ 542 cppr = ack & 0xff; 543 nsr = ack >> 8; 544 545 if (nsr & TM_QW1_NSR_EO) { 546 if (cppr == 0xff) 547 return; 548 /* Mark the priority pending */ 549 xc->pending_prio |= 1 << cppr; 550 551 /* 552 * A new interrupt should never have a CPPR less favored 553 * than our current one. 554 */ 555 if (cppr >= xc->cppr) 556 pr_err("CPU %d odd ack CPPR, got %d at %d\n", 557 smp_processor_id(), cppr, xc->cppr); 558 559 /* Update our idea of what the CPPR is */ 560 xc->cppr = cppr; 561 } 562 } 563 564 static void xive_spapr_eoi(u32 hw_irq) 565 { 566 /* Not used */; 567 } 568 569 static void xive_spapr_setup_cpu(unsigned int cpu, struct xive_cpu *xc) 570 { 571 /* Only some debug on the TIMA settings */ 572 pr_debug("(HW value: %08x %08x %08x)\n", 573 in_be32(xive_tima + TM_QW1_OS + TM_WORD0), 574 in_be32(xive_tima + TM_QW1_OS + TM_WORD1), 575 in_be32(xive_tima + TM_QW1_OS + TM_WORD2)); 576 } 577 578 static void xive_spapr_teardown_cpu(unsigned int cpu, struct xive_cpu *xc) 579 { 580 /* Nothing to do */; 581 } 582 583 static void xive_spapr_sync_source(u32 hw_irq) 584 { 585 /* Specs are unclear on what this is doing */ 586 plpar_int_sync(0, hw_irq); 587 } 588 589 static const struct xive_ops xive_spapr_ops = { 590 .populate_irq_data = xive_spapr_populate_irq_data, 591 .configure_irq = xive_spapr_configure_irq, 592 .setup_queue = xive_spapr_setup_queue, 593 .cleanup_queue = xive_spapr_cleanup_queue, 594 .match = xive_spapr_match, 595 .shutdown = xive_spapr_shutdown, 596 .update_pending = xive_spapr_update_pending, 597 .eoi = xive_spapr_eoi, 598 .setup_cpu = xive_spapr_setup_cpu, 599 .teardown_cpu = xive_spapr_teardown_cpu, 600 .sync_source = xive_spapr_sync_source, 601 .esb_rw = xive_spapr_esb_rw, 602 #ifdef CONFIG_SMP 603 .get_ipi = xive_spapr_get_ipi, 604 .put_ipi = xive_spapr_put_ipi, 605 #endif /* CONFIG_SMP */ 606 .name = "spapr", 607 }; 608 609 /* 610 * get max priority from "/ibm,plat-res-int-priorities" 611 */ 612 static bool xive_get_max_prio(u8 *max_prio) 613 { 614 struct device_node *rootdn; 615 const __be32 *reg; 616 u32 len; 617 int prio, found; 618 619 rootdn = of_find_node_by_path("/"); 620 if (!rootdn) { 621 pr_err("not root node found !\n"); 622 return false; 623 } 624 625 reg = of_get_property(rootdn, "ibm,plat-res-int-priorities", &len); 626 if (!reg) { 627 pr_err("Failed to read 'ibm,plat-res-int-priorities' property\n"); 628 return false; 629 } 630 631 if (len % (2 * sizeof(u32)) != 0) { 632 pr_err("invalid 'ibm,plat-res-int-priorities' property\n"); 633 return false; 634 } 635 636 /* HW supports priorities in the range [0-7] and 0xFF is a 637 * wildcard priority used to mask. We scan the ranges reserved 638 * by the hypervisor to find the lowest priority we can use. 639 */ 640 found = 0xFF; 641 for (prio = 0; prio < 8; prio++) { 642 int reserved = 0; 643 int i; 644 645 for (i = 0; i < len / (2 * sizeof(u32)); i++) { 646 int base = be32_to_cpu(reg[2 * i]); 647 int range = be32_to_cpu(reg[2 * i + 1]); 648 649 if (prio >= base && prio < base + range) 650 reserved++; 651 } 652 653 if (!reserved) 654 found = prio; 655 } 656 657 if (found == 0xFF) { 658 pr_err("no valid priority found in 'ibm,plat-res-int-priorities'\n"); 659 return false; 660 } 661 662 *max_prio = found; 663 return true; 664 } 665 666 bool __init xive_spapr_init(void) 667 { 668 struct device_node *np; 669 struct resource r; 670 void __iomem *tima; 671 struct property *prop; 672 u8 max_prio; 673 u32 val; 674 u32 len; 675 const __be32 *reg; 676 int i; 677 678 if (xive_cmdline_disabled) 679 return false; 680 681 pr_devel("%s()\n", __func__); 682 np = of_find_compatible_node(NULL, NULL, "ibm,power-ivpe"); 683 if (!np) { 684 pr_devel("not found !\n"); 685 return false; 686 } 687 pr_devel("Found %s\n", np->full_name); 688 689 /* Resource 1 is the OS ring TIMA */ 690 if (of_address_to_resource(np, 1, &r)) { 691 pr_err("Failed to get thread mgmnt area resource\n"); 692 return false; 693 } 694 tima = ioremap(r.start, resource_size(&r)); 695 if (!tima) { 696 pr_err("Failed to map thread mgmnt area\n"); 697 return false; 698 } 699 700 if (!xive_get_max_prio(&max_prio)) 701 return false; 702 703 /* Feed the IRQ number allocator with the ranges given in the DT */ 704 reg = of_get_property(np, "ibm,xive-lisn-ranges", &len); 705 if (!reg) { 706 pr_err("Failed to read 'ibm,xive-lisn-ranges' property\n"); 707 return false; 708 } 709 710 if (len % (2 * sizeof(u32)) != 0) { 711 pr_err("invalid 'ibm,xive-lisn-ranges' property\n"); 712 return false; 713 } 714 715 for (i = 0; i < len / (2 * sizeof(u32)); i++, reg += 2) 716 xive_irq_bitmap_add(be32_to_cpu(reg[0]), 717 be32_to_cpu(reg[1])); 718 719 /* Iterate the EQ sizes and pick one */ 720 of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, reg, val) { 721 xive_queue_shift = val; 722 if (val == PAGE_SHIFT) 723 break; 724 } 725 726 /* Initialize XIVE core with our backend */ 727 if (!xive_core_init(&xive_spapr_ops, tima, TM_QW1_OS, max_prio)) 728 return false; 729 730 pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10)); 731 return true; 732 } 733