1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2016,2017 IBM Corporation. 4 */ 5 6 #define pr_fmt(fmt) "xive: " fmt 7 8 #include <linux/types.h> 9 #include <linux/irq.h> 10 #include <linux/smp.h> 11 #include <linux/interrupt.h> 12 #include <linux/init.h> 13 #include <linux/of.h> 14 #include <linux/slab.h> 15 #include <linux/spinlock.h> 16 #include <linux/cpumask.h> 17 #include <linux/mm.h> 18 #include <linux/delay.h> 19 #include <linux/libfdt.h> 20 21 #include <asm/prom.h> 22 #include <asm/io.h> 23 #include <asm/smp.h> 24 #include <asm/irq.h> 25 #include <asm/errno.h> 26 #include <asm/xive.h> 27 #include <asm/xive-regs.h> 28 #include <asm/hvcall.h> 29 30 #include "xive-internal.h" 31 32 static u32 xive_queue_shift; 33 34 struct xive_irq_bitmap { 35 unsigned long *bitmap; 36 unsigned int base; 37 unsigned int count; 38 spinlock_t lock; 39 struct list_head list; 40 }; 41 42 static LIST_HEAD(xive_irq_bitmaps); 43 44 static int xive_irq_bitmap_add(int base, int count) 45 { 46 struct xive_irq_bitmap *xibm; 47 48 xibm = kzalloc(sizeof(*xibm), GFP_ATOMIC); 49 if (!xibm) 50 return -ENOMEM; 51 52 spin_lock_init(&xibm->lock); 53 xibm->base = base; 54 xibm->count = count; 55 xibm->bitmap = kzalloc(xibm->count, GFP_KERNEL); 56 list_add(&xibm->list, &xive_irq_bitmaps); 57 58 pr_info("Using IRQ range [%x-%x]", xibm->base, 59 xibm->base + xibm->count - 1); 60 return 0; 61 } 62 63 static int __xive_irq_bitmap_alloc(struct xive_irq_bitmap *xibm) 64 { 65 int irq; 66 67 irq = find_first_zero_bit(xibm->bitmap, xibm->count); 68 if (irq != xibm->count) { 69 set_bit(irq, xibm->bitmap); 70 irq += xibm->base; 71 } else { 72 irq = -ENOMEM; 73 } 74 75 return irq; 76 } 77 78 static int xive_irq_bitmap_alloc(void) 79 { 80 struct xive_irq_bitmap *xibm; 81 unsigned long flags; 82 int irq = -ENOENT; 83 84 list_for_each_entry(xibm, &xive_irq_bitmaps, list) { 85 spin_lock_irqsave(&xibm->lock, flags); 86 irq = __xive_irq_bitmap_alloc(xibm); 87 spin_unlock_irqrestore(&xibm->lock, flags); 88 if (irq >= 0) 89 break; 90 } 91 return irq; 92 } 93 94 static void xive_irq_bitmap_free(int irq) 95 { 96 unsigned long flags; 97 struct xive_irq_bitmap *xibm; 98 99 list_for_each_entry(xibm, &xive_irq_bitmaps, list) { 100 if ((irq >= xibm->base) && (irq < xibm->base + xibm->count)) { 101 spin_lock_irqsave(&xibm->lock, flags); 102 clear_bit(irq - xibm->base, xibm->bitmap); 103 spin_unlock_irqrestore(&xibm->lock, flags); 104 break; 105 } 106 } 107 } 108 109 110 /* Based on the similar routines in RTAS */ 111 static unsigned int plpar_busy_delay_time(long rc) 112 { 113 unsigned int ms = 0; 114 115 if (H_IS_LONG_BUSY(rc)) { 116 ms = get_longbusy_msecs(rc); 117 } else if (rc == H_BUSY) { 118 ms = 10; /* seems appropriate for XIVE hcalls */ 119 } 120 121 return ms; 122 } 123 124 static unsigned int plpar_busy_delay(int rc) 125 { 126 unsigned int ms; 127 128 ms = plpar_busy_delay_time(rc); 129 if (ms) 130 mdelay(ms); 131 132 return ms; 133 } 134 135 /* 136 * Note: this call has a partition wide scope and can take a while to 137 * complete. If it returns H_LONG_BUSY_* it should be retried 138 * periodically. 139 */ 140 static long plpar_int_reset(unsigned long flags) 141 { 142 long rc; 143 144 do { 145 rc = plpar_hcall_norets(H_INT_RESET, flags); 146 } while (plpar_busy_delay(rc)); 147 148 if (rc) 149 pr_err("H_INT_RESET failed %ld\n", rc); 150 151 return rc; 152 } 153 154 static long plpar_int_get_source_info(unsigned long flags, 155 unsigned long lisn, 156 unsigned long *src_flags, 157 unsigned long *eoi_page, 158 unsigned long *trig_page, 159 unsigned long *esb_shift) 160 { 161 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 162 long rc; 163 164 do { 165 rc = plpar_hcall(H_INT_GET_SOURCE_INFO, retbuf, flags, lisn); 166 } while (plpar_busy_delay(rc)); 167 168 if (rc) { 169 pr_err("H_INT_GET_SOURCE_INFO lisn=%ld failed %ld\n", lisn, rc); 170 return rc; 171 } 172 173 *src_flags = retbuf[0]; 174 *eoi_page = retbuf[1]; 175 *trig_page = retbuf[2]; 176 *esb_shift = retbuf[3]; 177 178 pr_devel("H_INT_GET_SOURCE_INFO flags=%lx eoi=%lx trig=%lx shift=%lx\n", 179 retbuf[0], retbuf[1], retbuf[2], retbuf[3]); 180 181 return 0; 182 } 183 184 #define XIVE_SRC_SET_EISN (1ull << (63 - 62)) 185 #define XIVE_SRC_MASK (1ull << (63 - 63)) /* unused */ 186 187 static long plpar_int_set_source_config(unsigned long flags, 188 unsigned long lisn, 189 unsigned long target, 190 unsigned long prio, 191 unsigned long sw_irq) 192 { 193 long rc; 194 195 196 pr_devel("H_INT_SET_SOURCE_CONFIG flags=%lx lisn=%lx target=%lx prio=%lx sw_irq=%lx\n", 197 flags, lisn, target, prio, sw_irq); 198 199 200 do { 201 rc = plpar_hcall_norets(H_INT_SET_SOURCE_CONFIG, flags, lisn, 202 target, prio, sw_irq); 203 } while (plpar_busy_delay(rc)); 204 205 if (rc) { 206 pr_err("H_INT_SET_SOURCE_CONFIG lisn=%ld target=%lx prio=%lx failed %ld\n", 207 lisn, target, prio, rc); 208 return rc; 209 } 210 211 return 0; 212 } 213 214 static long plpar_int_get_queue_info(unsigned long flags, 215 unsigned long target, 216 unsigned long priority, 217 unsigned long *esn_page, 218 unsigned long *esn_size) 219 { 220 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 221 long rc; 222 223 do { 224 rc = plpar_hcall(H_INT_GET_QUEUE_INFO, retbuf, flags, target, 225 priority); 226 } while (plpar_busy_delay(rc)); 227 228 if (rc) { 229 pr_err("H_INT_GET_QUEUE_INFO cpu=%ld prio=%ld failed %ld\n", 230 target, priority, rc); 231 return rc; 232 } 233 234 *esn_page = retbuf[0]; 235 *esn_size = retbuf[1]; 236 237 pr_devel("H_INT_GET_QUEUE_INFO page=%lx size=%lx\n", 238 retbuf[0], retbuf[1]); 239 240 return 0; 241 } 242 243 #define XIVE_EQ_ALWAYS_NOTIFY (1ull << (63 - 63)) 244 245 static long plpar_int_set_queue_config(unsigned long flags, 246 unsigned long target, 247 unsigned long priority, 248 unsigned long qpage, 249 unsigned long qsize) 250 { 251 long rc; 252 253 pr_devel("H_INT_SET_QUEUE_CONFIG flags=%lx target=%lx priority=%lx qpage=%lx qsize=%lx\n", 254 flags, target, priority, qpage, qsize); 255 256 do { 257 rc = plpar_hcall_norets(H_INT_SET_QUEUE_CONFIG, flags, target, 258 priority, qpage, qsize); 259 } while (plpar_busy_delay(rc)); 260 261 if (rc) { 262 pr_err("H_INT_SET_QUEUE_CONFIG cpu=%ld prio=%ld qpage=%lx returned %ld\n", 263 target, priority, qpage, rc); 264 return rc; 265 } 266 267 return 0; 268 } 269 270 static long plpar_int_sync(unsigned long flags, unsigned long lisn) 271 { 272 long rc; 273 274 do { 275 rc = plpar_hcall_norets(H_INT_SYNC, flags, lisn); 276 } while (plpar_busy_delay(rc)); 277 278 if (rc) { 279 pr_err("H_INT_SYNC lisn=%ld returned %ld\n", lisn, rc); 280 return rc; 281 } 282 283 return 0; 284 } 285 286 #define XIVE_ESB_FLAG_STORE (1ull << (63 - 63)) 287 288 static long plpar_int_esb(unsigned long flags, 289 unsigned long lisn, 290 unsigned long offset, 291 unsigned long in_data, 292 unsigned long *out_data) 293 { 294 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 295 long rc; 296 297 pr_devel("H_INT_ESB flags=%lx lisn=%lx offset=%lx in=%lx\n", 298 flags, lisn, offset, in_data); 299 300 do { 301 rc = plpar_hcall(H_INT_ESB, retbuf, flags, lisn, offset, 302 in_data); 303 } while (plpar_busy_delay(rc)); 304 305 if (rc) { 306 pr_err("H_INT_ESB lisn=%ld offset=%ld returned %ld\n", 307 lisn, offset, rc); 308 return rc; 309 } 310 311 *out_data = retbuf[0]; 312 313 return 0; 314 } 315 316 static u64 xive_spapr_esb_rw(u32 lisn, u32 offset, u64 data, bool write) 317 { 318 unsigned long read_data; 319 long rc; 320 321 rc = plpar_int_esb(write ? XIVE_ESB_FLAG_STORE : 0, 322 lisn, offset, data, &read_data); 323 if (rc) 324 return -1; 325 326 return write ? 0 : read_data; 327 } 328 329 #define XIVE_SRC_H_INT_ESB (1ull << (63 - 60)) 330 #define XIVE_SRC_LSI (1ull << (63 - 61)) 331 #define XIVE_SRC_TRIGGER (1ull << (63 - 62)) 332 #define XIVE_SRC_STORE_EOI (1ull << (63 - 63)) 333 334 static int xive_spapr_populate_irq_data(u32 hw_irq, struct xive_irq_data *data) 335 { 336 long rc; 337 unsigned long flags; 338 unsigned long eoi_page; 339 unsigned long trig_page; 340 unsigned long esb_shift; 341 342 memset(data, 0, sizeof(*data)); 343 344 rc = plpar_int_get_source_info(0, hw_irq, &flags, &eoi_page, &trig_page, 345 &esb_shift); 346 if (rc) 347 return -EINVAL; 348 349 if (flags & XIVE_SRC_H_INT_ESB) 350 data->flags |= XIVE_IRQ_FLAG_H_INT_ESB; 351 if (flags & XIVE_SRC_STORE_EOI) 352 data->flags |= XIVE_IRQ_FLAG_STORE_EOI; 353 if (flags & XIVE_SRC_LSI) 354 data->flags |= XIVE_IRQ_FLAG_LSI; 355 data->eoi_page = eoi_page; 356 data->esb_shift = esb_shift; 357 data->trig_page = trig_page; 358 359 /* 360 * No chip-id for the sPAPR backend. This has an impact how we 361 * pick a target. See xive_pick_irq_target(). 362 */ 363 data->src_chip = XIVE_INVALID_CHIP_ID; 364 365 data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift); 366 if (!data->eoi_mmio) { 367 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq); 368 return -ENOMEM; 369 } 370 371 data->hw_irq = hw_irq; 372 373 /* Full function page supports trigger */ 374 if (flags & XIVE_SRC_TRIGGER) { 375 data->trig_mmio = data->eoi_mmio; 376 return 0; 377 } 378 379 data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift); 380 if (!data->trig_mmio) { 381 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq); 382 return -ENOMEM; 383 } 384 return 0; 385 } 386 387 static int xive_spapr_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq) 388 { 389 long rc; 390 391 rc = plpar_int_set_source_config(XIVE_SRC_SET_EISN, hw_irq, target, 392 prio, sw_irq); 393 394 return rc == 0 ? 0 : -ENXIO; 395 } 396 397 /* This can be called multiple time to change a queue configuration */ 398 static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio, 399 __be32 *qpage, u32 order) 400 { 401 s64 rc = 0; 402 unsigned long esn_page; 403 unsigned long esn_size; 404 u64 flags, qpage_phys; 405 406 /* If there's an actual queue page, clean it */ 407 if (order) { 408 if (WARN_ON(!qpage)) 409 return -EINVAL; 410 qpage_phys = __pa(qpage); 411 } else { 412 qpage_phys = 0; 413 } 414 415 /* Initialize the rest of the fields */ 416 q->msk = order ? ((1u << (order - 2)) - 1) : 0; 417 q->idx = 0; 418 q->toggle = 0; 419 420 rc = plpar_int_get_queue_info(0, target, prio, &esn_page, &esn_size); 421 if (rc) { 422 pr_err("Error %lld getting queue info CPU %d prio %d\n", rc, 423 target, prio); 424 rc = -EIO; 425 goto fail; 426 } 427 428 /* TODO: add support for the notification page */ 429 q->eoi_phys = esn_page; 430 431 /* Default is to always notify */ 432 flags = XIVE_EQ_ALWAYS_NOTIFY; 433 434 /* Configure and enable the queue in HW */ 435 rc = plpar_int_set_queue_config(flags, target, prio, qpage_phys, order); 436 if (rc) { 437 pr_err("Error %lld setting queue for CPU %d prio %d\n", rc, 438 target, prio); 439 rc = -EIO; 440 } else { 441 q->qpage = qpage; 442 } 443 fail: 444 return rc; 445 } 446 447 static int xive_spapr_setup_queue(unsigned int cpu, struct xive_cpu *xc, 448 u8 prio) 449 { 450 struct xive_q *q = &xc->queue[prio]; 451 __be32 *qpage; 452 453 qpage = xive_queue_page_alloc(cpu, xive_queue_shift); 454 if (IS_ERR(qpage)) 455 return PTR_ERR(qpage); 456 457 return xive_spapr_configure_queue(get_hard_smp_processor_id(cpu), 458 q, prio, qpage, xive_queue_shift); 459 } 460 461 static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, 462 u8 prio) 463 { 464 struct xive_q *q = &xc->queue[prio]; 465 unsigned int alloc_order; 466 long rc; 467 int hw_cpu = get_hard_smp_processor_id(cpu); 468 469 rc = plpar_int_set_queue_config(0, hw_cpu, prio, 0, 0); 470 if (rc) 471 pr_err("Error %ld setting queue for CPU %d prio %d\n", rc, 472 hw_cpu, prio); 473 474 alloc_order = xive_alloc_order(xive_queue_shift); 475 free_pages((unsigned long)q->qpage, alloc_order); 476 q->qpage = NULL; 477 } 478 479 static bool xive_spapr_match(struct device_node *node) 480 { 481 /* Ignore cascaded controllers for the moment */ 482 return 1; 483 } 484 485 #ifdef CONFIG_SMP 486 static int xive_spapr_get_ipi(unsigned int cpu, struct xive_cpu *xc) 487 { 488 int irq = xive_irq_bitmap_alloc(); 489 490 if (irq < 0) { 491 pr_err("Failed to allocate IPI on CPU %d\n", cpu); 492 return -ENXIO; 493 } 494 495 xc->hw_ipi = irq; 496 return 0; 497 } 498 499 static void xive_spapr_put_ipi(unsigned int cpu, struct xive_cpu *xc) 500 { 501 if (!xc->hw_ipi) 502 return; 503 504 xive_irq_bitmap_free(xc->hw_ipi); 505 xc->hw_ipi = 0; 506 } 507 #endif /* CONFIG_SMP */ 508 509 static void xive_spapr_shutdown(void) 510 { 511 plpar_int_reset(0); 512 } 513 514 /* 515 * Perform an "ack" cycle on the current thread. Grab the pending 516 * active priorities and update the CPPR to the most favored one. 517 */ 518 static void xive_spapr_update_pending(struct xive_cpu *xc) 519 { 520 u8 nsr, cppr; 521 u16 ack; 522 523 /* 524 * Perform the "Acknowledge O/S to Register" cycle. 525 * 526 * Let's speedup the access to the TIMA using the raw I/O 527 * accessor as we don't need the synchronisation routine of 528 * the higher level ones 529 */ 530 ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_OS_REG)); 531 532 /* Synchronize subsequent queue accesses */ 533 mb(); 534 535 /* 536 * Grab the CPPR and the "NSR" field which indicates the source 537 * of the interrupt (if any) 538 */ 539 cppr = ack & 0xff; 540 nsr = ack >> 8; 541 542 if (nsr & TM_QW1_NSR_EO) { 543 if (cppr == 0xff) 544 return; 545 /* Mark the priority pending */ 546 xc->pending_prio |= 1 << cppr; 547 548 /* 549 * A new interrupt should never have a CPPR less favored 550 * than our current one. 551 */ 552 if (cppr >= xc->cppr) 553 pr_err("CPU %d odd ack CPPR, got %d at %d\n", 554 smp_processor_id(), cppr, xc->cppr); 555 556 /* Update our idea of what the CPPR is */ 557 xc->cppr = cppr; 558 } 559 } 560 561 static void xive_spapr_eoi(u32 hw_irq) 562 { 563 /* Not used */; 564 } 565 566 static void xive_spapr_setup_cpu(unsigned int cpu, struct xive_cpu *xc) 567 { 568 /* Only some debug on the TIMA settings */ 569 pr_debug("(HW value: %08x %08x %08x)\n", 570 in_be32(xive_tima + TM_QW1_OS + TM_WORD0), 571 in_be32(xive_tima + TM_QW1_OS + TM_WORD1), 572 in_be32(xive_tima + TM_QW1_OS + TM_WORD2)); 573 } 574 575 static void xive_spapr_teardown_cpu(unsigned int cpu, struct xive_cpu *xc) 576 { 577 /* Nothing to do */; 578 } 579 580 static void xive_spapr_sync_source(u32 hw_irq) 581 { 582 /* Specs are unclear on what this is doing */ 583 plpar_int_sync(0, hw_irq); 584 } 585 586 static const struct xive_ops xive_spapr_ops = { 587 .populate_irq_data = xive_spapr_populate_irq_data, 588 .configure_irq = xive_spapr_configure_irq, 589 .setup_queue = xive_spapr_setup_queue, 590 .cleanup_queue = xive_spapr_cleanup_queue, 591 .match = xive_spapr_match, 592 .shutdown = xive_spapr_shutdown, 593 .update_pending = xive_spapr_update_pending, 594 .eoi = xive_spapr_eoi, 595 .setup_cpu = xive_spapr_setup_cpu, 596 .teardown_cpu = xive_spapr_teardown_cpu, 597 .sync_source = xive_spapr_sync_source, 598 .esb_rw = xive_spapr_esb_rw, 599 #ifdef CONFIG_SMP 600 .get_ipi = xive_spapr_get_ipi, 601 .put_ipi = xive_spapr_put_ipi, 602 #endif /* CONFIG_SMP */ 603 .name = "spapr", 604 }; 605 606 /* 607 * get max priority from "/ibm,plat-res-int-priorities" 608 */ 609 static bool xive_get_max_prio(u8 *max_prio) 610 { 611 struct device_node *rootdn; 612 const __be32 *reg; 613 u32 len; 614 int prio, found; 615 616 rootdn = of_find_node_by_path("/"); 617 if (!rootdn) { 618 pr_err("not root node found !\n"); 619 return false; 620 } 621 622 reg = of_get_property(rootdn, "ibm,plat-res-int-priorities", &len); 623 if (!reg) { 624 pr_err("Failed to read 'ibm,plat-res-int-priorities' property\n"); 625 return false; 626 } 627 628 if (len % (2 * sizeof(u32)) != 0) { 629 pr_err("invalid 'ibm,plat-res-int-priorities' property\n"); 630 return false; 631 } 632 633 /* HW supports priorities in the range [0-7] and 0xFF is a 634 * wildcard priority used to mask. We scan the ranges reserved 635 * by the hypervisor to find the lowest priority we can use. 636 */ 637 found = 0xFF; 638 for (prio = 0; prio < 8; prio++) { 639 int reserved = 0; 640 int i; 641 642 for (i = 0; i < len / (2 * sizeof(u32)); i++) { 643 int base = be32_to_cpu(reg[2 * i]); 644 int range = be32_to_cpu(reg[2 * i + 1]); 645 646 if (prio >= base && prio < base + range) 647 reserved++; 648 } 649 650 if (!reserved) 651 found = prio; 652 } 653 654 if (found == 0xFF) { 655 pr_err("no valid priority found in 'ibm,plat-res-int-priorities'\n"); 656 return false; 657 } 658 659 *max_prio = found; 660 return true; 661 } 662 663 static const u8 *get_vec5_feature(unsigned int index) 664 { 665 unsigned long root, chosen; 666 int size; 667 const u8 *vec5; 668 669 root = of_get_flat_dt_root(); 670 chosen = of_get_flat_dt_subnode_by_name(root, "chosen"); 671 if (chosen == -FDT_ERR_NOTFOUND) 672 return NULL; 673 674 vec5 = of_get_flat_dt_prop(chosen, "ibm,architecture-vec-5", &size); 675 if (!vec5) 676 return NULL; 677 678 if (size <= index) 679 return NULL; 680 681 return vec5 + index; 682 } 683 684 static bool xive_spapr_disabled(void) 685 { 686 const u8 *vec5_xive; 687 688 vec5_xive = get_vec5_feature(OV5_INDX(OV5_XIVE_SUPPORT)); 689 if (vec5_xive) { 690 u8 val; 691 692 val = *vec5_xive & OV5_FEAT(OV5_XIVE_SUPPORT); 693 switch (val) { 694 case OV5_FEAT(OV5_XIVE_EITHER): 695 case OV5_FEAT(OV5_XIVE_LEGACY): 696 break; 697 case OV5_FEAT(OV5_XIVE_EXPLOIT): 698 /* Hypervisor only supports XIVE */ 699 if (xive_cmdline_disabled) 700 pr_warn("WARNING: Ignoring cmdline option xive=off\n"); 701 return false; 702 default: 703 pr_warn("%s: Unknown xive support option: 0x%x\n", 704 __func__, val); 705 break; 706 } 707 } 708 709 return xive_cmdline_disabled; 710 } 711 712 bool __init xive_spapr_init(void) 713 { 714 struct device_node *np; 715 struct resource r; 716 void __iomem *tima; 717 struct property *prop; 718 u8 max_prio; 719 u32 val; 720 u32 len; 721 const __be32 *reg; 722 int i; 723 724 if (xive_spapr_disabled()) 725 return false; 726 727 pr_devel("%s()\n", __func__); 728 np = of_find_compatible_node(NULL, NULL, "ibm,power-ivpe"); 729 if (!np) { 730 pr_devel("not found !\n"); 731 return false; 732 } 733 pr_devel("Found %s\n", np->full_name); 734 735 /* Resource 1 is the OS ring TIMA */ 736 if (of_address_to_resource(np, 1, &r)) { 737 pr_err("Failed to get thread mgmnt area resource\n"); 738 return false; 739 } 740 tima = ioremap(r.start, resource_size(&r)); 741 if (!tima) { 742 pr_err("Failed to map thread mgmnt area\n"); 743 return false; 744 } 745 746 if (!xive_get_max_prio(&max_prio)) 747 return false; 748 749 /* Feed the IRQ number allocator with the ranges given in the DT */ 750 reg = of_get_property(np, "ibm,xive-lisn-ranges", &len); 751 if (!reg) { 752 pr_err("Failed to read 'ibm,xive-lisn-ranges' property\n"); 753 return false; 754 } 755 756 if (len % (2 * sizeof(u32)) != 0) { 757 pr_err("invalid 'ibm,xive-lisn-ranges' property\n"); 758 return false; 759 } 760 761 for (i = 0; i < len / (2 * sizeof(u32)); i++, reg += 2) 762 xive_irq_bitmap_add(be32_to_cpu(reg[0]), 763 be32_to_cpu(reg[1])); 764 765 /* Iterate the EQ sizes and pick one */ 766 of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, reg, val) { 767 xive_queue_shift = val; 768 if (val == PAGE_SHIFT) 769 break; 770 } 771 772 /* Initialize XIVE core with our backend */ 773 if (!xive_core_init(&xive_spapr_ops, tima, TM_QW1_OS, max_prio)) 774 return false; 775 776 pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10)); 777 return true; 778 } 779